公开(公告)号：US10600871B2

公开(公告)日：2020-03-24

申请号：US15595643

申请日：2017-05-15

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/04 ,  H01L29/10 ,  H01L29/739 ,  H01L29/745 ,  H01L29/74

Abstract: The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter disclosed herein relates to shielding regions in the form of body region extensions for that reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed body region extensions have the same conductivity-type as the body region and extend outwardly from the body region and into the JFET region of a first device cell such that a distance between the body region extension and a region of a neighboring device cell having the same conductivity type is less than or equal to the parallel JFET width. The disclosed shielding regions enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

公开(公告)号：US10388737B2

公开(公告)日：2019-08-20

申请号：US15601754

申请日：2017-05-22

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/16 ,  H01L21/04 ,  H01L29/66 ,  H01L29/78 ,  H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/745 ,  H01L29/74

Abstract: The subject matter disclosed herein relates to silicon carbide (SiC) power devices. In particular, the present disclosure relates to shielding regions for use in combination with an optimization layer. The disclosed shielding regions reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed shielding regions occupy a portion of the JFET region between adjacent device cells and interrupt the continuity of the optimization layer in a widest portion of the JFET region, where the corners of neighboring device cells meet. The disclosed shielding regions and device layouts enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

公开(公告)号：US10347489B2

公开(公告)日：2019-07-09

申请号：US13933366

申请日：2013-07-02

Applicant: General Electric Company

Inventor： Peter Almern Losee ,  Alexander Viktorovich Bolotnikov ,  Stacey Joy Kennerly

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/06 ,  H01L29/74

Abstract: A method of manufacturing a semiconductor device is presented. The method includes providing a semiconductor layer comprising silicon carbide, wherein the semiconductor layer comprises a first region doped with a first dopant type. The method further includes implanting the semiconductor layer with a second dopant type using a single implantation mask and a substantially similar implantation dose to form a second region and a junction termination extension (JTE) in the semiconductor layer, wherein the implantation dose is in a range from about 2×1013 cm−2 to about 12×1013 cm−2. Semiconductor devices are also presented.

公开(公告)号：US20190088479A1

公开(公告)日：2019-03-21

申请号：US15953037

申请日：2018-04-13

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee ,  Reza Ghandi ,  David Alan Lilienfeld

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/36 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

Abstract: A method of manufacturing a semiconductor device including performing a first implantation in a semiconductor layer via ion implantation forming a first implantation region and performing a second implantation in the semiconductor layer via ion implantation forming a second implantation region. The first and second implantation overlap with one another and combine to form a connection region extending into the semiconductor layer by a predefined depth.

公开(公告)号：US10211304B2

公开(公告)日：2019-02-19

申请号：US14097075

申请日：2013-12-04

Applicant: General Electric Company

Inventor： Peter Almern Losee ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/423 ,  H01L29/16 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/417 ,  H01L23/544 ,  H01L29/04 ,  H01L29/06

Abstract: The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.). A semiconductor device includes a well region extending a first depth into a surface of an epitaxial semiconductor layer positioned above a drift region. The device includes a junction field-effect transistor (JFET) region positioned adjacent to the well region in the epitaxial semiconductor layer. The device also includes a trench extending a second depth into the JFET region, wherein the trench comprises a bottom and a sidewall that extends down to the bottom at an angle relative to the surface of the epitaxial semiconductor layer.

公开(公告)号：US10199465B2

公开(公告)日：2019-02-05

申请号：US14313820

申请日：2014-06-24

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/76 ,  H01L29/10 ,  H01L29/08 ,  H01L29/16 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L29/739 ,  H01L29/06

Abstract: A method of fabricating a semiconductor device cell at a surface of a silicon carbide (SiC) semiconductor layer includes forming a segmented source and body contact (SSBC) of the semiconductor device cell over the surface of the SiC semiconductor layer. The SSBC includes a body contact portion disposed over the surface of the semiconductor layer and proximate to a body contact region of the semiconductor device cell, wherein the body contact portion is not disposed over the center of the semiconductor device cell. The SSBC also includes a source contact portion disposed over the surface of the semiconductor layer and proximate to a source contact region of the semiconductor device cell, wherein the at least one source contact portion only partially surrounds the body contact portion of the SSBC.

公开(公告)号：US20170338313A1

公开(公告)日：2017-11-23

申请号：US15595611

申请日：2017-05-15

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/16 ,  H01L29/66 ,  H01L21/04 ,  H01L29/78 ,  H01L29/06 ,  H01L29/74 ,  H01L29/739

CPC classification number: H01L29/1608 ,  H01L21/046 ,  H01L21/0465 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0646 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66068 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/7455 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7816

Abstract: The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter disclosed herein relates to disconnected or connected shielding regions that reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed shielding regions occupy a widest portion of the JFET region between adjacent device cells such that a distance between a shielding region and well regions surrounding device cell is less than a parallel JFET width between two adjacent device cells, while maintaining a channel region width and/or a JFET region density that is greater than that of a comparable conventional stripe device. As such, the disclosed shielding regions and device layouts enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

公开(公告)号：US20170338300A1

公开(公告)日：2017-11-23

申请号：US15595717

申请日：2017-05-15

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/06 ,  H01L29/745 ,  H01L29/66 ,  H01L21/04 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L29/739

CPC classification number: H01L29/1608 ,  H01L21/046 ,  H01L21/0465 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0646 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66068 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/7455 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7816

Abstract: The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter disclosed herein relates to shielding regions in the form of channel region extensions for that reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed channel region extensions have the same conductivity-type as the channel region and extend outwardly from the channel region and into the JFET region of a first device cell such that a distance between the channel region extension and a region of a neighboring device cell having the same conductivity type is less than or equal to the parallel JFET width. The disclosed shielding regions enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

公开(公告)号：US20170278924A1

公开(公告)日：2017-09-28

申请号：US15077579

申请日：2016-03-22

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee ,  David Alan Lilienfeld ,  Reza Ghandi

IPC: H01L29/06 ,  H01L21/04 ,  H01L29/808 ,  H01L29/73 ,  H01L29/78 ,  H01L29/16 ,  H01L29/861

CPC classification number: H01L29/0634 ,  H01L21/046 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66272 ,  H01L29/66909 ,  H01L29/73 ,  H01L29/732 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/808 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/872

Abstract: A super junction (SJ) device may include one or more charge balance (CB) layers. Each CB layer may include an epitaxial (epi) layer having a first conductivity type and a plurality of charge balance (CB) regions having a second conductivity type. Additionally, the SJ device may include a connection region having the second conductivity type that extends from a region disposed in a top surface of a device layer of the SJ device to one or more of the CB regions. The connection region may enable carriers to flow directly from the region to the one or more CB regions, which may decrease switching losses of the SJ device.

公开(公告)号：US20160380059A1

公开(公告)日：2016-12-29

申请号：US14752446

申请日：2015-06-26

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Peter Almern Losee ,  Alexander Viktorovich Bolotnikov ,  Reza Ghandi

IPC: H01L29/16 ,  H01L21/04 ,  H01L29/06

CPC classification number: H01L29/1608 ,  H01L29/0634 ,  H01L29/6606 ,  H01L29/8083 ,  H01L29/872

Abstract: The subject matter disclosed herein relates to silicon carbide (SiC) power devices and, more specifically, to active area designs for SiC super-junction (SJ) power devices. A SiC-SJ device includes an active area having one or more charge balance (CB) layers. Each CB layer includes a semiconductor layer having a first conductivity-type and a plurality of floating regions having a second conductivity-type disposed in a surface of the semiconductor layer. The plurality of floating regions and the semiconductor layer are both configured to substantially deplete to provide substantially equal amounts of charge from ionized dopants when a reverse bias is applied to the SiC-SJ device.

Abstract translation: 本文公开的主题涉及碳化硅（SiC）功率器件，更具体地，涉及用于SiC超结（SJ）功率器件的有源区域设计。 SiC-SJ器件包括具有一个或多个电荷平衡（CB）层的有源区。 每个CB层包括具有第一导电类型的半导体层和设置在半导体层的表面中的具有第二导电类型的多个浮动区域。 当将反向偏压施加到SiC-SJ器件时，多个浮动区域和半导体层都被配置为基本上耗尽以提供基本相等量的电离掺杂剂的电荷。