公开(公告)号：US09121890B2

公开(公告)日：2015-09-01

申请号：US14067204

申请日：2013-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sipeng Gu ,  Xiang Hu ,  Alok Vaid ,  Lokesh Subramany ,  Akshey Sehgal

IPC: H01L21/311 ,  H01L21/302 ,  G01R31/26 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L22/30 ,  G01R31/2621 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924

Abstract: Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area.

Abstract translation: 公开了一种用于提供具有与翅片场效应晶体管（FinFET）器件的一组翅片相邻的平面度量垫的衬底的方法。 具体地说，FinFET器件包括鳍式衬底和在FinFET器件的度量测量区域中与衬底相邻的衬底上形成的平面度量垫。 处理步骤包括在衬底上形成第一硬掩模，在FinFET器件的测量测量区域中的第一硬掩模的一部分上形成光致抗蚀剂，在形成光致抗蚀剂之后，在与测量测量区域相邻的区域中残留的部分去除第一硬掩模 在衬底中图案化一组开口以在邻近测量测量区域的区域中的FinFET器件中形成一组鳍片，在FinFET器件上沉积氧化物层，以及平坦化FinFET器件，以形成平面度量板 计量测量领域。

公开(公告)号：US20150069515A1

公开(公告)日：2015-03-12

申请号：US14023558

申请日：2013-09-11

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xiang Hu ,  Jin Ping Liu ,  Jill Hildreth ,  Taejoon Han

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/845

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a fin structure overlying a semiconductor substrate. The fin structure defines a fin axis extending in a longitudinal direction perpendicular to a lateral direction and has two fin sidewalls parallel to the fin axis. The method includes forming gate structures overlying the fin structure and transverse to the fin axis. Further, the method includes growing an epitaxial material on the fin structure and confining growth of the epitaxial material in the lateral direction.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，一种用于制造集成电路的方法包括提供覆盖半导体衬底的翅片结构。 翅片结构限定了在垂直于横向方向的纵向方向上延伸的翅片轴线，并且具有平行于翅片轴线的两个翅片侧壁。 该方法包括形成覆盖翅片结构并横向于翅片轴线的栅极结构。 此外，该方法包括在翅片结构上生长外延材料并限制外延材料在横向上的生长。

公开(公告)号：US20140120708A1

公开(公告)日：2014-05-01

申请号：US13664744

申请日：2012-10-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Michael P. Chudzik ,  Min Dai ,  Xiang Hu ,  Jinping Liu ,  Yanxiang Liu ,  Xiaodong Yang

IPC: H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/2807 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/823462

Abstract: A method of manufacturing a semiconductor device including a replacement metal gate process incorporating a conductive dummy gate layer (e.g., silicon germanium (SiGe), titanium nitride, etc.) and a related are disclosed. The method includes forming an oxide layer on a substrate; removing a gate portion of the oxide layer from the substrate in a first region of the semiconductor device; forming a conductive dummy gate layer on the semiconductor device in the first region; and forming a gate on the semiconductor device, the gate including a gate conductor disposed in the first region and directly connected to the substrate.

Abstract translation: 公开了一种制造半导体器件的方法，该半导体器件包括结合导电虚拟栅极层（例如硅锗（SiGe），氮化钛等）的替代金属栅极工艺）和相关的方法。 该方法包括在衬底上形成氧化物层; 在所述半导体器件的第一区域中从所述衬底去除所述氧化物层的栅极部分; 在所述第一区域中的所述半导体器件上形成导电虚拟栅极层; 以及在所述半导体器件上形成栅极，所述栅极包括设置在所述第一区域中并直接连接到所述衬底的栅极导体。