公开(公告)号：US08835292B2

公开(公告)日：2014-09-16

申请号：US13664744

申请日：2012-10-31

申请人： International Business Machines Corporation ,  Globalfoundries Inc.

发明人： Michael P. Chudzik ,  Min Dai ,  Xiang Hu ,  Jinping Liu ,  Yanxiang Liu ,  Xiaodong Yang

IPC分类号： H01L21/3205

CPC分类号： H01L29/66545 ,  H01L21/2807 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/823462

摘要： A method of manufacturing a semiconductor device including a replacement metal gate process incorporating a conductive dummy gate layer (e.g., silicon germanium (SiGe), titanium nitride, etc.) and a related are disclosed. The method includes forming an oxide layer on a substrate; removing a gate portion of the oxide layer from the substrate in a first region of the semiconductor device; forming a conductive dummy gate layer on the semiconductor device in the first region; and forming a gate on the semiconductor device, the gate including a gate conductor disposed in the first region and directly connected to the substrate.

摘要翻译： 公开了一种制造半导体器件的方法，该半导体器件包括结合导电虚拟栅极层（例如硅锗（SiGe），氮化钛等）的替代金属栅极工艺）和相关的方法。 该方法包括在衬底上形成氧化物层; 在所述半导体器件的第一区域中从所述衬底去除所述氧化物层的栅极部分; 在所述第一区域中的所述半导体器件上形成导电虚拟栅极层; 以及在所述半导体器件上形成栅极，所述栅极包括设置在所述第一区域中并直接连接到所述衬底的栅极导体。

公开(公告)号：US20140120708A1

公开(公告)日：2014-05-01

申请号：US13664744

申请日：2012-10-31

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

发明人： Michael P. Chudzik ,  Min Dai ,  Xiang Hu ,  Jinping Liu ,  Yanxiang Liu ,  Xiaodong Yang

IPC分类号： H01L21/28

CPC分类号： H01L29/66545 ,  H01L21/2807 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/823462

摘要： A method of manufacturing a semiconductor device including a replacement metal gate process incorporating a conductive dummy gate layer (e.g., silicon germanium (SiGe), titanium nitride, etc.) and a related are disclosed. The method includes forming an oxide layer on a substrate; removing a gate portion of the oxide layer from the substrate in a first region of the semiconductor device; forming a conductive dummy gate layer on the semiconductor device in the first region; and forming a gate on the semiconductor device, the gate including a gate conductor disposed in the first region and directly connected to the substrate.

摘要翻译： 公开了一种制造半导体器件的方法，该半导体器件包括结合导电虚拟栅极层（例如硅锗（SiGe），氮化钛等）的替代金属栅极工艺）和相关的方法。 该方法包括在衬底上形成氧化物层; 在所述半导体器件的第一区域中从所述衬底去除所述氧化物层的栅极部分; 在所述第一区域中的所述半导体器件上形成导电虚拟栅极层; 以及在所述半导体器件上形成栅极，所述栅极包括设置在所述第一区域中并直接连接到所述衬底的栅极导体。

公开(公告)号：US10121711B2

公开(公告)日：2018-11-06

申请号：US14816708

申请日：2015-08-03

申请人： GLOBALFOUNDRIES Inc.

发明人： Sipeng Gu ,  Xiang Hu ,  Alok Vaid ,  Lokesh Subramany ,  Akshey Sehgal

IPC分类号： H01L29/10 ,  H01L29/76 ,  H01L21/82 ,  H01L21/66 ,  G01R31/26 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092

摘要： Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area.

公开(公告)号：US09817927B2

公开(公告)日：2017-11-14

申请号：US14841037

申请日：2015-08-31

申请人： GLOBALFOUNDRIES Inc.

发明人： Guo Xiang Ning ,  Yuping Ren ,  David Power ,  Lalit Shokeen ,  Chin Teong Lim ,  Paul W. Ackmann ,  Xiang Hu

IPC分类号： G06F17/50 ,  G03F1/36

CPC分类号： G06F17/5009 ,  G03F1/36 ,  G06F17/5081

摘要： A method and apparatus for generating a final dielectric etch compensation table and a final hard mask etch compensation table for either OPC or MPC process flows are provided. Embodiments include performing an overlap pattern classification on a wafer; calibrating a dielectric etch bias or a hard mask etch bias based on the pattern classification; comparing either a CD overlap of a via layer with a metal layer and a CD overlap of the via layer with a lower connecting metal layer or a CD overlap of the metal layer with an upper connecting via layer and a CD overlap of the metal layer with the via layer against a criteria; outputting final dielectric etch compensation and hard mask etch compensation tables to either OPC or MPC process flows; and repeating the steps of calibrating, comparing, and outputting for either the via layer or metal layer remaining.

公开(公告)号：US09460963B2

公开(公告)日：2016-10-04

申请号：US14225529

申请日：2014-03-26

申请人： GLOBALFOUNDRIES Inc.

发明人： Gabriel Padron Wells ,  Xiang Hu ,  Guillaume Bouche ,  Andre Labonte

IPC分类号： H01L21/467 ,  H01L21/768 ,  H01L29/40 ,  H01L21/033 ,  H01L21/308 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8234

CPC分类号： H01L21/76897 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/467 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795

摘要： Embodiments of the present invention provide an improved contact and method of fabrication. A dielectric layer is formed over transistor structures which include gates and source/drain regions. A first etch, which may be a reactive ion etch, is used to partially recess the dielectric layer. A second etch is then used to continue the etch of the dielectric layer to form a cavity adjacent to the gate spacers. The second etch is highly selective to the spacer material, which prevents damage to the spacers during the exposure (opening) of the source/drain regions.

摘要翻译： 本发明的实施例提供了改进的接触和制造方法。 在包括栅极和源极/漏极区域的晶体管结构上形成介电层。 使用可以是反应离子蚀刻的第一蚀刻来部分地凹陷介电层。 然后使用第二蚀刻来继续蚀刻介电层以形成与栅极间隔物相邻的空腔。 第二蚀刻对间隔物材料具有高选择性，这防止了在源极/漏极区域的曝光（打开）期间损坏间隔物。

公开(公告)号：US09236301B2

公开(公告)日：2016-01-12

申请号：US13939322

申请日：2013-07-11

申请人： GLOBALFOUNDRIES Inc.

发明人： Guoxiang Ning ,  Xiang Hu ,  Paul Ackmann ,  Sarasvathi Thangaraju

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L23/48

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： Fabrication of through-substrate via (TSV) structures is facilitated by: forming at least one stress buffer within a substrate; forming a through-substrate via contact within the substrate, wherein the through-substrate via structure and the stress buffer(s) are disposed adjacent to or in contact with each other; and where the stress buffer(s) includes a configuration or is disposed at a location relative to the through-substrate via conductor, at least in part, according to whether the TSV structure is an isolated TSV structure, a chained TSV structure, or an arrayed TSV structure, to customize stress alleviation by the stress buffer(s) about the through-substrate via conductor based, at least in part, on the type of TSV structure.

摘要翻译： 通过（TSV）结构制造贯穿衬底通过以下方式促进：在衬底内形成至少一个应力缓冲液; 通过所述衬底内的接触形成贯通衬底，其中所述贯通衬底通孔结构和所述应力缓冲器被设置为彼此相邻或接触; 并且其中所述应力缓冲器包括配置或者被布置在相对于所述贯通基板通孔导体的位置处，至少部分地根据所述TSV结构是否是隔离的TSV结构，链接的TSV结构或 至少部分地基于TSV结构的类型来定义通过基于导体的贯穿衬底的应力缓冲器的应力缓解。

公开(公告)号：US20150340296A1

公开(公告)日：2015-11-26

申请号：US14816708

申请日：2015-08-03

申请人： GLOBALFOUNDRIES Inc.

发明人： Sipeng Gu ,  Xiang Hu ,  Alok Vaid ,  Lokesh Subramany ,  Akshey Sehgal

IPC分类号： H01L21/66 ,  H01L27/088

CPC分类号： H01L22/30 ,  G01R31/2621 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924

摘要： Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area.

摘要翻译： 公开了一种用于提供具有与翅片场效应晶体管（FinFET）器件的一组翅片相邻的平面度量垫的衬底的方法。 具体地说，FinFET器件包括鳍式衬底和在FinFET器件的度量测量区域中与衬底相邻的衬底上形成的平面度量垫。 处理步骤包括在衬底上形成第一硬掩模，在FinFET器件的测量测量区域中的第一硬掩模的一部分上形成光致抗蚀剂，在形成光致抗蚀剂之后，在与测量测量区域相邻的区域中残留的部分去除第一硬掩模 在衬底中图案化一组开口以在邻近测量测量区域的区域中的FinFET器件中形成一组鳍片，在FinFET器件上沉积氧化物层，以及平坦化FinFET器件，以形成平面度量板 计量测量领域。

公开(公告)号：US09040380B2

公开(公告)日：2015-05-26

申请号：US14023558

申请日：2013-09-11

申请人： GLOBALFOUNDRIES, Inc.

发明人： Xiang Hu ,  Jin Ping Liu ,  Jill Hildreth ,  Taejoon Han

IPC分类号： H01L21/336 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823431 ,  H01L21/845

摘要： Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a fin structure overlying a semiconductor substrate. The fin structure defines a fin axis extending in a longitudinal direction perpendicular to a lateral direction and has two fin sidewalls parallel to the fin axis. The method includes forming gate structures overlying the fin structure and transverse to the fin axis. Further, the method includes growing an epitaxial material on the fin structure and confining growth of the epitaxial material in the lateral direction.

摘要翻译： 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，一种用于制造集成电路的方法包括提供覆盖半导体衬底的翅片结构。 翅片结构限定了在垂直于横向方向的纵向方向上延伸的翅片轴线，并且具有平行于翅片轴线的两个翅片侧壁。 该方法包括形成覆盖翅片结构并横向于翅片轴线的栅极结构。 此外，该方法包括在翅片结构上生长外延材料并限制外延材料在横向上的生长。

公开(公告)号：US08877642B2

公开(公告)日：2014-11-04

申请号：US13756689

申请日：2013-02-01

申请人： GLOBALFOUNDRIES Inc.

发明人： Xiang Hu

IPC分类号： H01L21/02 ,  H01L21/66 ,  H01L21/302 ,  H01L21/28 ,  H01L21/033 ,  H01L29/66 ,  H01L21/82

CPC分类号： H01L21/28008 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/32139 ,  H01L21/82 ,  H01L21/823828 ,  H01L22/12 ,  H01L22/20 ,  H01L29/66545

摘要： Fabricating of one or more semiconductor devices with critical gate dimension control is facilitated by: providing a multilayer stack structure over a substrate; etching through the multilayer stack structure, with critical gate dimension control, to define multiple gate lines; providing a protective layer over the multiple gate lines; and patterning and cutting one or more gate lines of the multiple gate lines to facilitate defining multiple gate structures of the one or more semiconductor devices. Etching through the multilayer stack structure is facilitated by lithographically patterning the multilayer stack structure, and critical dimension feedback control is provided to at least one of the lithographically patterning or the etching through the multilayer stack structure.

摘要翻译： 通过在衬底上提供多层堆叠结构来促进具有临界栅极尺寸控制的一个或多个半导体器件的制造; 通过具有关键栅极尺寸控制的多层堆叠结构蚀刻以限定多条栅极线; 在多个栅极线上提供保护层; 以及图案化和切割所述多个栅极线的一个或多个栅极线以便于限定所述一个或多个半导体器件的多个栅极结构。 通过对多层堆叠结构进行光刻图案来促进通过多层堆叠结构的蚀刻，并且通过多层堆叠结构提供至少一个光刻图案或蚀刻的临界尺寸反馈控制。

公开(公告)号：US20160043081A1

公开(公告)日：2016-02-11

申请号：US14918012

申请日：2015-10-20

申请人： GLOBALFOUNDRIES Inc.

发明人： Andy Chih-Hung Wei ,  Dae-han Choi ,  Dae Geun Yang ,  Xiang Hu ,  Mariappan Hariharaputhiran

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/311 ,  H01L29/06 ,  H01L21/308 ,  H01L21/02

CPC分类号： H01L27/0886 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/475 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/785

摘要： Embodiments of the present invention provide methods of removing fin portions from a finFET. At a starting point, a high-K dielectric layer is disposed on a substrate. A fin hardmask and lithography stack is deposited on the high-k dielectric. A fin hardmask is exposed, and a first portion of the fin hardmark is removed. The lithography stack is removed. A second portion of the fin hardmask is removed. Fins are formed. A gap fill dielectric is deposited and recessed.