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    Concurrently Forming nFET and pFET Gate Dielectric Layers
    1.
    发明申请
    Concurrently Forming nFET and pFET Gate Dielectric Layers 有权
    并联形成nFET和pFET栅介质层

    公开(公告)号：US20140187028A1

    公开(公告)日：2014-07-03

    申请号：US13732455

    申请日：2013-01-02

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

    发明人： Takashi Ando ,  Maryjane Brodsky ,  Michael P. Chudzik ,  Min Dai ,  Siddarth A. Krishnan ,  Joseph F. Shepard, JR. ,  Yanfeng Wang ,  Jinping Liu

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823857

    摘要： Embodiments include methods of forming an nFET-tuned gate dielectric and a pFET-tuned gate dielectric. Methods may include forming a high-k layer above a substrate having a pFET region and an nFET region, forming a first sacrificial layer, a pFET work-function metal layer, and a second sacrificial layer above the first high-k layer in the pFET region, and an nFET work-function metal layer above the first high-k layer in the nFET region and above the second sacrificial layer in the pFET region. The first high-k layer then may be annealed to form an nFET gate dielectric layer in the nFET region and a pFET gate dielectric layer in the pFET region. The first high-k layer may be annealed in the presence of a nitrogen source to cause atoms from the nitrogen source to diffuse into the first high-k layer in the nFET region.

    摘要翻译： 实施例包括形成nFET调谐的栅极电介质和pFET调谐的栅极电介质的方法。 方法可以包括在pFET区域和nFET区域上形成高k层，形成第一牺牲层，pFET功函数金属层和在pFET中的第一高k层上方的第二牺牲层 区域，以及在nFET区域中的第一高k层上方的nFET功函数金属层，并且在pFET区域中的第二牺牲层上方。 第一高k层然后可以退火以在nFET区域中形成nFET栅极介电层，并在pFET区域中形成pFET栅极电介质层。 第一高k层可以在存在氮源的情况下进行退火，以使来自氮源的原子扩散到nFET区域中的第一高k层。

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING REPLACEMENT METAL GATE PROCESS INCORPORATING A CONDUCTIVE DUMMY GATE LAYER
    2.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING REPLACEMENT METAL GATE PROCESS INCORPORATING A CONDUCTIVE DUMMY GATE LAYER 有权
    制造半导体器件的方法，包括更换金属栅极工艺，包括导电的DUMMY GATE层

    公开(公告)号：US20140120708A1

    公开(公告)日：2014-05-01

    申请号：US13664744

    申请日：2012-10-31

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

    发明人： Michael P. Chudzik ,  Min Dai ,  Xiang Hu ,  Jinping Liu ,  Yanxiang Liu ,  Xiaodong Yang

    IPC分类号： H01L21/28

    CPC分类号： H01L29/66545 ,  H01L21/2807 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/823462

    摘要： A method of manufacturing a semiconductor device including a replacement metal gate process incorporating a conductive dummy gate layer (e.g., silicon germanium (SiGe), titanium nitride, etc.) and a related are disclosed. The method includes forming an oxide layer on a substrate; removing a gate portion of the oxide layer from the substrate in a first region of the semiconductor device; forming a conductive dummy gate layer on the semiconductor device in the first region; and forming a gate on the semiconductor device, the gate including a gate conductor disposed in the first region and directly connected to the substrate.

    摘要翻译： 公开了一种制造半导体器件的方法，该半导体器件包括结合导电虚拟栅极层（例如硅锗（SiGe），氮化钛等）的替代金属栅极工艺）和相关的方法。 该方法包括在衬底上形成氧化物层; 在所述半导体器件的第一区域中从所述衬底去除所述氧化物层的栅极部分; 在所述第一区域中的所述半导体器件上形成导电虚拟栅极层; 以及在所述半导体器件上形成栅极，所述栅极包括设置在所述第一区域中并直接连接到所述衬底的栅极导体。

    Method of manufacturing semiconductor devices including replacement metal gate process incorporating a conductive dummy gate layer
    3.
    发明授权
    Method of manufacturing semiconductor devices including replacement metal gate process incorporating a conductive dummy gate layer 有权
    包括具有导电虚拟栅极层的替代金属栅极工艺的半导体器件的制造方法

    公开(公告)号：US08835292B2

    公开(公告)日：2014-09-16

    申请号：US13664744

    申请日：2012-10-31

    申请人： International Business Machines Corporation ,  Globalfoundries Inc.

    发明人： Michael P. Chudzik ,  Min Dai ,  Xiang Hu ,  Jinping Liu ,  Yanxiang Liu ,  Xiaodong Yang

    IPC分类号： H01L21/3205

    CPC分类号： H01L29/66545 ,  H01L21/2807 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/823462

    摘要： A method of manufacturing a semiconductor device including a replacement metal gate process incorporating a conductive dummy gate layer (e.g., silicon germanium (SiGe), titanium nitride, etc.) and a related are disclosed. The method includes forming an oxide layer on a substrate; removing a gate portion of the oxide layer from the substrate in a first region of the semiconductor device; forming a conductive dummy gate layer on the semiconductor device in the first region; and forming a gate on the semiconductor device, the gate including a gate conductor disposed in the first region and directly connected to the substrate.

    摘要翻译： 公开了一种制造半导体器件的方法，该半导体器件包括结合导电虚拟栅极层（例如硅锗（SiGe），氮化钛等）的替代金属栅极工艺）和相关的方法。 该方法包括在衬底上形成氧化物层; 在所述半导体器件的第一区域中从所述衬底去除所述氧化物层的栅极部分; 在所述第一区域中的所述半导体器件上形成导电虚拟栅极层; 以及在所述半导体器件上形成栅极，所述栅极包括设置在所述第一区域中并直接连接到所述衬底的栅极导体。

    Concurrently forming nFET and pFET gate dielectric layers
    4.
    发明授权
    Concurrently forming nFET and pFET gate dielectric layers 有权
    同时形成nFET和pFET栅极电介质层

    公开(公告)号：US09059315B2

    公开(公告)日：2015-06-16

    申请号：US13732455

    申请日：2013-01-02

    申请人： International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

    发明人： Takashi Ando ,  Maryjane Brodsky ,  Michael P. Chudzik ,  Min Dai ,  Siddarth A. Krishnan ,  Joseph F. Shepard, Jr. ,  Yanfeng Wang ,  Jinping Liu

    IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/8238

    CPC分类号： H01L21/823857

    摘要： Embodiments include methods of forming an nFET-tuned gate dielectric and a pFET-tuned gate dielectric. Methods may include forming a high-k layer above a substrate having a pFET region and an nFET region, forming a first sacrificial layer, a pFET work-function metal layer, and a second sacrificial layer above the first high-k layer in the pFET region, and an nFET work-function metal layer above the first high-k layer in the nFET region and above the second sacrificial layer in the pFET region. The first high-k layer then may be annealed to form an nFET gate dielectric layer in the nFET region and a pFET gate dielectric layer in the pFET region. The first high-k layer may be annealed in the presence of a nitrogen source to cause atoms from the nitrogen source to diffuse into the first high-k layer in the nFET region.

    摘要翻译： 实施例包括形成nFET调谐的栅极电介质和pFET调谐的栅极电介质的方法。 方法可以包括在pFET区域和nFET区域之上形成高k层，形成第一牺牲层，pFET功函数金属层和在pFET中的第一高k层上方的第二牺牲层 区域，以及在nFET区域中的第一高k层上方的nFET功函数金属层，并且在pFET区域中的第二牺牲层上方。 第一高k层然后可以退火以在nFET区域中形成nFET栅极介电层，并在pFET区域中形成pFET栅极电介质层。 第一高k层可以在存在氮源的情况下进行退火，以使来自氮源的原子扩散到nFET区域中的第一高k层。

    Structure and method of Tinv scaling for high k metal gate technology
    9.
    发明授权
    Structure and method of Tinv scaling for high k metal gate technology 有权
    用于高k金属栅极技术的Tinv缩放的结构和方法

    公开(公告)号：US09087784B2

    公开(公告)日：2015-07-21

    申请号：US14167532

    申请日：2014-01-29

    申请人： International Business Machines Corporation

    发明人： Michael P. Chudzik ,  Dechao Guo ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Carl J. Radens ,  Shahab Siddiqui

    IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L27/092

    CPC分类号： H01L21/28008 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

    摘要： A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) is provided. Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. The pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack may also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and an nFET threshold voltage adjusted species located therein.

    摘要翻译： 提供包括缩放的n沟道场效应晶体管（nFET）和缩放的p沟道场效应晶体管（pFET）的互补金属氧化物半导体（CMOS）结构。 通过在nFET栅极堆叠内形成等离子体氮化的nFET阈值电压调整的高k栅极电介质层部分，以及在pFET栅极堆叠内形成至少pFET阈值电压调整的高k栅介质层部分来提供这种结构。 pFET栅极堆叠中的pFET阈值电压调节的高k栅介质层部分也可以等离子体氮化。 等离子体氮化nFET阈值电压调节的高k栅极电介质层部分包括高达15原子％的N 2和位于其中的nFET阈值电压调节的物质。

    Replacement gate having work function at valence band edge
    10.
    发明授权
    Replacement gate having work function at valence band edge 有权
    在价带边缘具有功函数的替换门

    公开(公告)号：US09059313B2

    公开(公告)日：2015-06-16

    申请号：US13770552

    申请日：2013-02-19

    申请人： International Business Machines Corporation

    发明人： Keith Kwong Hon Wong ,  Michael P. Chudzik ,  Unoh Kwon

    IPC分类号： H01L21/8238 ,  H01L29/51 ,  H01L29/165 ,  H01L29/49 ,  H01L29/78 ,  H01L29/66

    CPC分类号： H01L21/823842 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

    摘要： Replacement gate stacks are provided, which increase the work function of the gate electrode of a p-type field effect transistor (PFET). In one embodiment, the work function metal stack includes a titanium-oxide-nitride layer located between a lower titanium nitride layer and an upper titanium nitride layer. The stack of the lower titanium nitride layer, the titanium-oxide-nitride layer, and the upper titanium nitride layer produces the unexpected result of increasing the work function of the work function metal stack significantly. In another embodiment, the work function metal stack includes an aluminum layer deposited at a temperature not greater than 420° C. The aluminum layer deposited at a temperature not greater than 420° C. produces the unexpected result of increasing the work function of the work function metal stack significantly.

    摘要翻译： 提供了替代栅极堆叠，这增加了p型场效应晶体管（PFET）的栅电极的功函数。 在一个实施例中，功函数金属堆叠包括位于下部氮化钛层和上部氮化钛层之间的氧化钛 - 氮化物层。 下部氮化钛层，钛氧化物 - 氮化物层和上部氮化钛层的堆叠产生显着增加功函数金属叠层功函数的意想不到的结果。 在另一个实施例中，功函数金属堆叠包括在不高于420℃的温度下沉积的铝层。在不高于420℃的温度下沉积的铝层产生增加工件功函数的意想不到的结果 功能金属堆叠显着。