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公开(公告)号：US08609461B1
公开(公告)日：2013-12-17
申请号：US12777907
申请日：2010-05-11
IPC分类号： H01L29/72
CPC分类号： H01L29/1602 , H01L21/02376 , H01L21/02546 , H01L21/02587 , H01L21/02658 , H01L21/02664 , H01L21/2007
摘要： Various embodiments provide methods for forming a diamond heat spreader and integrating the diamond heat spreader with a heat source without generating voids at the interface. In one embodiment, a semiconductor layer can be epitaxially formed on a diamond substrate having a desirably low surface root mean square (RMS) roughness. The semiconductor epi-layer can be used as an interface layer for bonding the diamond substrate to the heat source to provide efficient heat spreading.
摘要翻译： 各种实施例提供了用于形成金刚石散热器并将金刚石散热器与热源集成而不在界面处产生空隙的方法。 在一个实施例中，可以在具有期望的低表面均方根（RMS）粗糙度的金刚石基底上外延形成半导体层。 半导体外延层可以用作将金刚石基底结合到热源的界面层，以提供有效的散热。
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42.发明申请公开(公告)号：US20130297853A1
公开(公告)日：2013-11-07
申请号：US13464084
申请日：2012-05-04
申请人： Ganesh Balakrishnan , Anil Krishna
发明人： Ganesh Balakrishnan , Anil Krishna
IPC分类号： G06F12/00
CPC分类号： G06F12/0866 , G06F12/0246 , G06F2212/222 , G06F2212/40 , Y02D10/13
摘要： In a method for storing data in a flash memory array, the flash memory array includes a plurality of physical pages. The method includes receiving a request to perform a data access operation through a communication bus. The request includes data and a logical page address. The method further includes allocating one or more physical pages of the flash memory array to perform the data access operation. The method further includes, based on a historical usage data of the flash memory array, selectively encoding the data contained in the logical page into the one or more physical pages.
摘要翻译： 在将数据存储在闪存阵列中的方法中，闪存阵列包括多个物理页。 该方法包括通过通信总线接收执行数据访问操作的请求。 该请求包括数据和逻辑页面地址。 该方法还包括分配闪存阵列的一个或多个物理页面以执行数据访问操作。 该方法还包括基于闪速存储器阵列的历史使用数据，选择性地将包含在逻辑页面中的数据编码到一个或多个物理页面中。
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公开(公告)号：US08572325B2
公开(公告)日：2013-10-29
申请号：US12961798
申请日：2010-12-07
IPC分类号： G06F12/08
CPC分类号： G06F12/0871 , G06F2212/282
摘要： Embodiments of the invention are directed to optimizing the performance of a split disk cache. In one embodiment, a disk cache includes a primary region having a read portion and write portion and one or more smaller, sample regions also including a read portion and a write portion. The primary region and one or more sample region each have an independently adjustable ratio of a read portion to a write portion. Cached reads are distributed among the read portions of the primary and sample region, while cached writes are distributed among the write portions of the primary and sample region. The performance of the primary region and the performance of the sample region are tracked, such as by obtaining a hit rate for each region during a predefined interval. The read/write ratio of the primary region is then selectively adjusted according to the performance of the one or more sample regions.
摘要翻译： 本发明的实施例旨在优化分割盘高速缓存的性能。 在一个实施例中，磁盘高速缓存包括具有读取部分和写入部分的主区域以及还包括读取部分和写入部分的一个或多个更小的采样区域。 主区域和一个或多个采样区域各自具有读取部分与写入部分的独立可调比率。 高速缓存的读取分布在主要和采样区域的读取部分之间，而高速缓存的写入分布在主要和样本区域的写入部分之间。 跟踪主区域的性能和样本区域的性能，例如通过在预定义的间隔期间获得每个区域的命中率。 然后根据一个或多个样品区域的性能选择性地调节主区域的读/写比。
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公开(公告)号：US08482465B1
公开(公告)日：2013-07-09
申请号：US13004004
申请日：2011-01-10
IPC分类号： H01Q1/36
摘要： Various embodiments provide materials and methods for an optically pumped switch device, an optically pumped reconfigurable antenna system (OPRAS), and their related antenna devices. In one embodiment, the switch devices and the antenna devices can have a photoconductive cell. The photoconductive cell can include a semiconductive substrate that is conductive to reflect a radio frequency (RF) signal in response to an optical signal.
摘要翻译： 各种实施例提供了用于光泵浦开关装置，光泵浦可重构天线系统（OPRAS）及其相关天线装置的材料和方法。 在一个实施例中，开关装置和天线装置可以具有光导电池。 光导电池可以包括导电的半导体衬底，以响应于光信号反射射频（RF）信号。
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公开(公告)号：US08364898B2
公开(公告)日：2013-01-29
申请号：US12358873
申请日：2009-01-23
申请人： Ganesh Balakrishnan , Anil Krishna
发明人： Ganesh Balakrishnan , Anil Krishna
CPC分类号： G06F12/0802 , G06F12/0808 , G06F12/0811 , G06F12/0864 , G06F12/123
摘要： A method and a system for utilizing less recently used (LRU) bits and presence bits in selecting cache-lines for eviction from a lower level cache in a processor-memory sub-system. A cache back invalidation (CBI) logic utilizes LRU bits to evict only cache-lines within a LRU group, following a cache miss in the lower level cache. In addition, the CBI logic uses presence bits to (a) indicate whether a cache-line in a lower level cache is also present in a higher level cache and (b) evict only cache-lines in the lower level cache that are not present in a corresponding higher level cache. However, when the lower level cache-line selected for eviction is also present in any higher level cache, CBI logic invalidates the cache-line in the higher level cache. The CBI logic appropriately updates the values of presence bits and LRU bits, following evictions and invalidations.
摘要翻译： 一种用于利用最近使用的（LRU）比特和存在比特来选择用于从处理器存储器子系统中的较低级高速缓存进行逐出的高速缓存线的方法和系统。 缓存返回无效（CBI）逻辑利用LRU位来驱逐LRU组内的高速缓存行，跟随低级缓存中的高速缓存未命中。 此外，CBI逻辑使用存在位来（a）指示较低级高速缓存中的高速缓存行是否也存在于较高级高速缓存中，并且（b）仅驱逐不存在的较低级高速缓存中的高速缓存行 在相应的较高级缓存中。 然而，当选择用于逐出的较低级高速缓存行也存在于任何更高级别的高速缓存中时，CBI逻辑使高级缓存中的高速缓存行无效。 驱逐和无效后，CBI逻辑适当地更新存在位和LRU位的值。
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公开(公告)号：US08140825B2
公开(公告)日：2012-03-20
申请号：US12185964
申请日：2008-08-05
CPC分类号： G06F12/0215
摘要： Systems, methods and media for selectively closing pages in a memory in anticipation of a context switch are disclosed. In one embodiment, a table is provided to keep track of open pages for different processes. The table comprises rows corresponding to banks of memory and columns corresponding to cores of a multi-core processing system. When a context switch signal is received, the system unsets a bit in a column corresponding to the core from which the process is to be context-switched out. If no other process is using a page opened by the process the page is closed.
摘要翻译： 公开了用于在预期上下文切换中选择性地关闭存储器中的页面的系统，方法和介质。 在一个实施例中，提供了用于跟踪不同进程的打开页面的表格。 该表包括与多核处理系统的核心相对应的存储体组和列的行。 当接收到上下文切换信号时，系统取消对应于该进程将上下文切换出的核心的列中的位。 如果没有其他进程正在使用页面打开的页面关闭。
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47.发明授权Hybrid integration based on wafer-bonding of devices to AlSb monolithically grown on Si 有权基于硅片上单晶硅生长的AlSb器件的晶圆结合的混合集成公开(公告)号：US07700395B2
公开(公告)日：2010-04-20
申请号：US11622306
申请日：2007-01-11
IPC分类号： H01L21/00
CPC分类号： H01L21/187 , H01S5/0215 , H01S5/028 , H01S5/183
摘要： Exemplary embodiments provide a semiconductor fabrication method including a combination of monolithic integration techniques with wafer bonding techniques. The resulting semiconductor devices can be used in a wide variety of opto-electronic and/or electronic applications such as lasers, light emitting diodes (LEDs), phototvoltaics, photodetectors and transistors. In an exemplary embodiment, the semiconductor device can be formed by first forming an active-device structure including an active-device section disposed on a thinned III-V substrate. The active-device section can include OP and/or EP VCSEL devices. A high-quality monolithic integration structure can then be formed with low defect density through an interfacial misfit dislocation. In the high-quality monolithic integration structure, a thinned III-V mating layer can be formed over a silicon substrate. The thinned III-V substrate of the active-device structure can subsequently be wafer-bonded onto the thinned III-V mating layer of the high-quality monolithic integration structure forming an optoelectronic semiconductor device on silicon.
摘要翻译： 示例性实施例提供了包括单片集成技术与晶片接合技术的组合的半导体制造方法。 所得到的半导体器件可以用于各种光电子和/或电子应用中，例如激光器，发光二极管（LED），光伏电池，光电检测器和晶体管。 在示例性实施例中，半导体器件可以通过首先形成有源器件结构来形成，该有源器件结构包括设置在薄化III-V衬底上的有源器件部分。 有源器件部分可以包括OP和/或EP VCSEL器件。 然后可以通过界面失配位错形成具有低缺陷密度的高质量单片整合结构。 在高质量的单块集成结构中，可以在硅衬底上形成薄的III-V配合层。 有源器件结构的薄化III-V衬底可以随后被晶片结合到在硅上形成光电半导体器件的高质量单片集成结构的薄化III-V配合层上。
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公开(公告)号：US20100037034A1
公开(公告)日：2010-02-11
申请号：US12185964
申请日：2008-08-05
IPC分类号： G06F12/10
CPC分类号： G06F12/0215
摘要： Systems, methods and media for selectively closing pages in a memory in anticipation of a context switch are disclosed. In one embodiment, a table is provided to keep track of open pages for different processes. The table comprises rows corresponding to banks of memory and columns corresponding to cores of a multi-core processing system. When a context switch signal is received, the system unsets a bit in a column corresponding to the core from which the process is to be context-switched out. If no other process is using a page opened by the process the page is closed.
摘要翻译： 公开了用于在预期上下文切换中选择性地关闭存储器中的页面的系统，方法和介质。 在一个实施例中，提供了用于跟踪不同进程的打开页面的表格。 该表包括与多核处理系统的核心相对应的存储体组和列的行。 当接收到上下文切换信号时，系统取消对应于该进程将上下文切换出的核心的列中的位。 如果没有其他进程正在使用页面打开的页面关闭。
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公开(公告)号：US20080133864A1
公开(公告)日：2008-06-05
申请号：US11566149
申请日：2006-12-01
IPC分类号： G06F12/06
CPC分类号： G06F12/0811 , G06F12/0804
摘要： An apparatus, system, and method are disclosed for caching fully buffered memory (FBM) data. A circuit card is connected to an FBM socket that is configured to receive a FBM. An interface module communicates with a memory controller and at least one FBM via the FBM socket through a plurality of electrical interfaces. A cache controller apportions memory space in the cache memory between each FBM of the at least one FBM according to an apportionment policy. A cache memory transparently stores data from the at least one FBM and the memory controller and transparently provides the data to the memory controller. The cache controller manages coherency between the at least one FBM and the cache memory.
摘要翻译： 公开了用于缓存全缓冲存储器（FBM）数据的装置，系统和方法。 电路卡连接到配置为接收FBM的FBM插座。 接口模块通过多个电接口经由FBM插座与存储器控制器和至少一个FBM通信。 缓存控制器根据分配策略来分配至少一个FBM的每个FBM之间的高速缓冲存储器中的存储器空间。 缓存存储器透明地存储来自至少一个FBM和存储器控制器的数据，并将数据透明地提供给存储器控制器。 高速缓存控制器管理至少一个FBM和高速缓冲存储器之间的一致性。
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