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公开(公告)号：US20080203438A1
公开(公告)日：2008-08-28
申请号：US12114857
申请日：2008-05-05
IPC分类号： H01L27/10 , G11C17/08 , H01L21/8239
CPC分类号： H01L27/228 , G11C13/0004 , H01L21/84 , H01L27/24 , H01L29/785
摘要： A demultiplexer using transistors for accessing memory cell arrays. The demultiplexer includes (a) a substrate; (b) 2N semiconductor regions which are parallel to one another and run in a first direction; (c) first N gate electrode lines, which (i) run in a second direction which is perpendicular to the first direction, (ii) are electrically insulated from the 2N semiconductor regions, and (iii) are disposed between the first plurality of memory cells and the contact region; (d) a contact region; (e) a first plurality of memory cells. An intersection transistor exists at each of intersections between the first N gate electrode lines and the 2N semiconductor regions. In response to pre-specified voltage potentials being applied to the contact region and the first N gate electrode lines, memory cells of the first plurality of memory cells disposed on only one of the 2N semiconductor regions are selected.
摘要翻译： 一种使用晶体管访问存储单元阵列的解复用器。 解复用器包括（a）衬底; （b）彼此平行并在第一方向上延伸的N + N个半导体区域; （c）第一N栅电极线，其（i）沿与第一方向垂直的第二方向延伸，（ii）与二极管半导体区域电绝缘，以及（iii） 设置在所述第一多个存储单元和所述接触区域之间; （d）接触区域; （e）第一多个存储单元。 在第一N个栅极电极线和2个N个半导体区域之间的每个交叉处存在交叉晶体管。 响应于施加到接触区域和前N个栅电极线的预定电压电势，选择仅设置在2个N个半导体区域中的一个半导体区域上的第一多个存储单元的存储单元 。
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42.发明申请MULTI-BIT HIGH-DENSITY MEMORY DEVICE AND ARCHITECTURE AND METHOD OF FABRICATING MULTI-BIT HIGH-DENSITY MEMORY DEVICES 有权多位高密度存储器件和架构以及制造多位高密度存储器件的方法公开(公告)号：US20080001176A1
公开(公告)日：2008-01-03
申请号：US11427487
申请日：2006-06-29
CPC分类号： H01L27/0207 , B82Y10/00 , H01L27/115 , H01L29/0665 , H01L29/0673 , H01L29/42336 , H01L29/785 , Y10S438/947 , Y10S977/888 , Y10S977/936
摘要： A structure, memory devices using the structure, and methods of fabricating the structure. The structure includes: an array of nano-fins, each nano-fin comprising an elongated block of semiconductor material extending axially along a first direction, the nano-fins arranged in groups of at least two nano-fins each, wherein ends of nano-fins of each adjacent group of nano-fins are staggered with respect to each other on both a first and a second side of the array; wherein nano-fins of each group of nano-fins are electrically connected to a common contact that is specific to each group of nano-fins such that the common contacts comprise a first common contact on the first side of the array and a second common contact on the second side of the array; and wherein each group of nano-fins has at least two gates that electrically control the conductance of nano-fins of the each group of nano-fins.
摘要翻译： 一种结构，使用该结构的存储器件以及该结构的制造方法。 该结构包括：纳米鳍片阵列，每个纳米鳍片包括沿着第一方向轴向延伸的细长的半导体材料块，所述纳米鳍片分别以至少两个纳米翅片的组排列，其中， 每个相邻组的纳米翅片的翅片在阵列的第一和第二侧上彼此交错; 其中每组纳米鳍片的纳米鳍片电连接到对于每组纳米鳍片特有的公共接触点，使得所述公共接触件包括在所述阵列的第一侧上的第一公共接触点和第二公共接触点 在阵列的第二面; 并且其中每组纳米鳍具有至少两个门，其电控制每组纳米鳍的纳米鳍的电导。
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43.发明授权Decoding scheme for bipolar-based diode three-dimensional memory requiring unipolar programming 有权需要单极编程的双极型二极管三维存储器的解码方案公开(公告)号：US08902690B2
公开(公告)日：2014-12-02
申请号：US13584423
申请日：2012-08-13
IPC分类号： G11C8/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0023 , G11C13/0038 , G11C13/004 , G11C2213/71 , G11C2213/72
摘要： A system and method for operating a unipolar memory cell array including a bidirectional access diode. An example embodiment is a method including determining if the operating state of the unipolar memory cell is in a select state or a deselect state and the programming state is a read state or a write state. The method switches a column voltage switch based on the operating state and the programming state of the unipolar memory cell. The method further switches a row voltage switch based on the operating state and the programming state of the unipolar memory cell.
摘要翻译： 一种用于操作包括双向存取二极管的单极存储单元阵列的系统和方法。 示例性实施例是一种方法，包括确定单极存储器单元的操作状态是处于选择状态还是取消选择状态，并且编程状态是读取状态或写入状态。 该方法根据单极性存储单元的工作状态和编程状态切换列电压开关。 该方法还基于单极存储器单元的操作状态和编程状态来切换行电压开关。
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公开(公告)号：US20130039110A1
公开(公告)日：2013-02-14
申请号：US13209405
申请日：2011-08-14
申请人： Chung H. Lam , Jing Li , Kailash Gopalakrishnan
发明人： Chung H. Lam , Jing Li , Kailash Gopalakrishnan
CPC分类号： G11C13/00 , G11C5/02 , G11C7/00 , G11C11/16 , G11C11/22 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C13/0023 , G11C13/0069 , G11C2013/0073 , G11C2213/71 , H01L27/224 , H01L27/2409 , H01L45/04 , H01L45/06 , H01L45/146 , H01L45/147 , H01L45/16
摘要： Memory device and method for fabricating a memory device on two layers of a semiconductor wafer. An example device includes bit lines and word lines fabricated at one layer of a semiconductor wafer and re-writable nonvolatile memory cells that include a two-terminal access device with a bidirectional voltage-current characteristics for positive and negative voltages applied at the terminals. Additionally, a drive circuit electrically coupled to the memory cells and configured to program the memory cells is fabricated at another layer of the semiconductor wafer. Another example embodiment includes a memory device where a plurality of memory arrays are fabricated at one layer of a semiconductor wafer and a plurality of drive circuits electrically coupled to the memory cells and configured to read the memory cells are fabricated at a second layer of the semiconductor wafer.
摘要翻译： 用于在两层半导体晶片上制造存储器件的存储器件和方法。 示例性器件包括在半导体晶片的一个层处制造的位线和字线以及包括具有用于在端子处施加的正电压和负电压的双向电压 - 电流特性的双端子存取器件的可重写非易失性存储器单元。 此外，在半导体晶片的另一层处制造电耦合到存储器单元并被配置为对存储器单元进行编程的驱动电路。 另一示例性实施例包括存储器件，其中在半导体晶片的一个层处制造多个存储器阵列，并且电耦合到存储器单元并被配置为读取存储器单元的多个驱动电路在半导体的第二层处制造 晶圆。
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45.发明申请Crosspoint Array and Method of Use with a Crosspoint Array Having Crossbar Elements Having a Solid Electrolyte Material Used as a Rectifier with a Symmetric or Substantially Symmetric Resistive Memory 有权交叉点阵列和交叉点阵列的使用方法，其具有用作具有对称或基本对称的电阻存储器的整流器的固体电解质材料的交叉元件公开(公告)号：US20120243291A1
公开(公告)日：2012-09-27
申请号：US13487427
申请日：2012-06-04
CPC分类号： H01L27/2409 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C13/0007 , G11C13/0011 , G11C13/003 , G11C13/0069 , G11C2013/0073 , G11C2213/31 , G11C2213/32 , G11C2213/51 , G11C2213/71 , G11C2213/72 , G11C2213/76 , H01L27/224
摘要： A crosspoint array has been shown having a plurality of bitlines and wordlines; and a plurality of crossbar elements, with each crossbar element being disposed between a bitline and a wordline and with each crossbar element having at least a solid electrolyte material used as a rectifier in series with a symmetric or substantially symmetric resistive memory node. The crossbar elements are responsive to the following voltages: a first set of voltages to transition the solid electrolyte in the crossbar elements from an OFF state to an ON state, a second set of voltages to read or program the symmetric resistive memory, and a third set of voltages to transition solid electrolyte from an ON state to an OFF state.
摘要翻译： 已经示出了具有多个位线和字线的交叉点阵列; 以及多个横杆元件，其中每个横杆元件设置在位线和字线之间，并且每个横杆元件至少具有用作与对称或基本上对称的电阻性存储器节点串联的整流器的固体电解质材料。 交叉开关元件响应于以下电压：将交叉开关元件中的固体电解质从OFF状态转变到导通状态的第一组电压，用于读取或编程对称电阻性存储器的第二组电压，以及第三组 一组电压将固体电解质从ON状态转变为OFF状态。
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公开(公告)号：US08114723B2
公开(公告)日：2012-02-14
申请号：US12794826
申请日：2010-06-07
IPC分类号： H01L21/84
CPC分类号： H01L27/0207 , B82Y10/00 , H01L27/115 , H01L29/0665 , H01L29/0673 , H01L29/42336 , H01L29/785 , Y10S438/947 , Y10S977/888 , Y10S977/936
摘要： A structure, memory devices using the structure, and methods of fabricating the structure. The structure includes: an array of nano-fins, each nano-fin comprising an elongated block of semiconductor material extending axially along a first direction, the nano-fins arranged in groups of at least two nano-fins each, wherein ends of nano-fins of each adjacent group of nano-fins are staggered with respect to each other on both a first and a second side of the array; wherein nano-fins of each group of nano-fins are electrically connected to a common contact that is specific to each group of nano-fins such that the common contacts comprise a first common contact on the first side of the array and a second common contact on the second side of the array; and wherein each group of nano-fins has at least two gates that electrically control the conductance of nano-fins of the each group of nano-fins.
摘要翻译： 一种结构，使用该结构的存储器件以及该结构的制造方法。 该结构包括：纳米鳍片阵列，每个纳米鳍片包括沿着第一方向轴向延伸的细长的半导体材料块，所述纳米鳍片分别以至少两个纳米翅片的组排列，其中， 每个相邻组的纳米翅片的翅片在阵列的第一和第二侧上彼此交错; 其中每组纳米鳍片的纳米鳍片电连接到对于每组纳米鳍片特有的公共接触点，使得所述公共接触件包括在所述阵列的第一侧上的第一公共接触点和第二共同接触点 在阵列的第二面; 并且其中每组纳米鳍具有至少两个门，其电控制每组纳米鳍的纳米鳍的电导。
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公开(公告)号：US07829926B2
公开(公告)日：2010-11-09
申请号：US12114857
申请日：2008-05-05
IPC分类号： H01L27/108
CPC分类号： H01L27/228 , G11C13/0004 , H01L21/84 , H01L27/24 , H01L29/785
摘要： A demultiplexer using transistors for accessing memory cell arrays. The demultiplexer includes (a) a substrate; (b) 2N semiconductor regions which are parallel to one another and run in a first direction; (c) first N gate electrode lines, which (i) run in a second direction which is perpendicular to the first direction, (ii) are electrically insulated from the 2N semiconductor regions, and (iii) are disposed between the first plurality of memory cells and the contact region; (d) a contact region; (e) a first plurality of memory cells. An intersection transistor exists at each of intersections between the first N gate electrode lines and the 2N semiconductor regions. In response to pre-specified voltage potentials being applied to the contact region and the first N gate electrode lines, memory cells of the first plurality of memory cells disposed on only one of the 2N semiconductor regions are selected.
摘要翻译： 一种使用晶体管访问存储单元阵列的解复用器。 解复用器包括（a）衬底; （b）2N个彼此平行并沿第一方向延伸的半导体区域; （c）第一N栅电极线，其（i）沿与第一方向垂直的第二方向延伸，（ii）与2N个半导体区域电绝缘，并且（iii）设置在第一多个存储器 细胞和接触区域; （d）接触区域; （e）第一多个存储单元。 在第一N个栅电极线和2N个半导体区之间的交点处存在交叉晶体管。 响应于施加到接触区域和前N个栅电极线的预定电压电势，选择仅设置在2N个半导体区域中的一个上的第一多个存储单元的存储单元。
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公开(公告)号：US07692244B2
公开(公告)日：2010-04-06
申请号：US11926025
申请日：2007-10-28
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L27/1203 , G11C16/08 , H01L21/84 , H01L27/115 , Y10S977/936 , Y10S977/938 , Y10S977/958
摘要： An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array.
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公开(公告)号：US07514327B2
公开(公告)日：2009-04-07
申请号：US11926031
申请日：2007-10-28
IPC分类号： H01L21/84
CPC分类号： H01L27/1203 , G11C16/08 , H01L21/84 , H01L27/115 , Y10S977/936 , Y10S977/938 , Y10S977/958
摘要： An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array.
摘要翻译： 电子扫描复用设备能够寻址易失性或非易失性存储器单元内的多个位。 多路复用装置产生具有两个相对形成的耗尽区的电子扫描导电通道。 每个耗尽区的耗尽宽度由施加到多路复用器件每端的相应控制栅极的电压控制。 目前的多位寻址技术允许例如在单个节点上访问或寻址10到100位的数据。 本发明还可用于构建可编程纳米尺度逻辑阵列或用于随机访问纳米级传感器阵列。
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公开(公告)号：US20080251840A1
公开(公告)日：2008-10-16
申请号：US11926025
申请日：2007-10-28
IPC分类号： H01L29/76
CPC分类号： H01L27/1203 , G11C16/08 , H01L21/84 , H01L27/115 , Y10S977/936 , Y10S977/938 , Y10S977/958
摘要： An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array.
摘要翻译： 电子扫描复用设备能够寻址易失性或非易失性存储器单元内的多个位。 多路复用装置产生具有两个相对形成的耗尽区的电子扫描导电通道。 每个耗尽区的耗尽宽度由施加到多路复用器件每端的相应控制栅极的电压控制。 目前的多位寻址技术允许例如在单个节点上访问或寻址10到100位的数据。 本发明还可用于构建可编程纳米尺度逻辑阵列或用于随机访问纳米级传感器阵列。
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