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1.发明授权Multi-bit high-density memory device and architecture and method of fabricating multi-bit high-density memory devices 有权多位高密度存储器件，以及制造多位高密度存储器件的架构和方法公开(公告)号：US07763932B2
公开(公告)日：2010-07-27
申请号：US11427487
申请日：2006-06-29
IPC分类号： H01L27/115
CPC分类号： H01L27/0207 , B82Y10/00 , H01L27/115 , H01L29/0665 , H01L29/0673 , H01L29/42336 , H01L29/785 , Y10S438/947 , Y10S977/888 , Y10S977/936
摘要： A structure, memory devices using the structure, and methods of fabricating the structure. The structure includes: an array of nano-fins, each nano-fin comprising an elongated block of semiconductor material extending axially along a first direction, the nano-fins arranged in groups of at least two nano-fins each, wherein ends of nano-fins of each adjacent group of nano-fins are staggered with respect to each other on both a first and a second side of the array; wherein nano-fins of each group of nano-fins are electrically connected to a common contact that is specific to each group of nano-fins such that the common contacts comprise a first common contact on the first side of the array and a second common contact on the second side of the array; and wherein each group of nano-fins has at least two gates that electrically control the conductance of nano-fins of the each group of nano-fins.
摘要翻译： 一种结构，使用该结构的存储器件以及该结构的制造方法。 该结构包括：纳米鳍片阵列，每个纳米鳍片包括沿着第一方向轴向延伸的细长的半导体材料块，所述纳米鳍片分别以至少两个纳米翅片的组排列，其中， 每个相邻组的纳米翅片的翅片在阵列的第一和第二侧上彼此相交; 其中每组纳米鳍片的纳米鳍片电连接到对于每组纳米鳍片特有的公共接触点，使得所述公共接触件包括在所述阵列的第一侧上的第一公共接触点和第二公共接触点 在阵列的第二面; 并且其中每组纳米鳍具有至少两个门，其电控制每组纳米鳍的纳米鳍的电导。
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2.发明申请MULTI-BIT HIGH-DENSITY MEMORY DEVICE AND ARCHITECTURE AND METHOD OF FABRICATING MULTI-BIT HIGH-DENSITY MEMORY DEVICES 有权多位高密度存储器件和架构以及制造多位高密度存储器件的方法公开(公告)号：US20100248441A1
公开(公告)日：2010-09-30
申请号：US12794826
申请日：2010-06-07
IPC分类号： H01L21/425 , H01L21/20
CPC分类号： H01L27/0207 , B82Y10/00 , H01L27/115 , H01L29/0665 , H01L29/0673 , H01L29/42336 , H01L29/785 , Y10S438/947 , Y10S977/888 , Y10S977/936
摘要： A structure, memory devices using the structure, and methods of fabricating the structure. The structure includes: an array of nano-fins, each nano-fin comprising an elongated block of semiconductor material extending axially along a first direction, the nano-fins arranged in groups of at least two nano-fins each, wherein ends of nano-fins of each adjacent group of nano-fins are staggered with respect to each other on both a first and a second side of the array; wherein nano-fins of each group of nano-fins are electrically connected to a common contact that is specific to each group of nano-fins such that the common contacts comprise a first common contact on the first side of the array and a second common contact on the second side of the array; and wherein each group of nano-fins has at least two gates that electrically control the conductance of nano-fins of the each group of nano-fins.
摘要翻译： 一种结构，使用该结构的存储器件以及该结构的制造方法。 该结构包括：纳米鳍片阵列，每个纳米鳍片包括沿着第一方向轴向延伸的细长的半导体材料块，所述纳米鳍片分别以至少两个纳米翅片的组排列，其中， 每个相邻组的纳米翅片的翅片在阵列的第一和第二侧上彼此交错; 其中每组纳米鳍片的纳米鳍片电连接到对于每组纳米鳍片特有的公共接触点，使得所述公共接触件包括在所述阵列的第一侧上的第一公共接触点和第二共同接触点 在阵列的第二面; 并且其中每组纳米鳍具有至少两个门，其电控制每组纳米鳍的纳米鳍的电导。
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公开(公告)号：US20080054306A1
公开(公告)日：2008-03-06
申请号：US11468512
申请日：2006-08-30
IPC分类号： H01L27/10
CPC分类号： H01L27/228 , G11C13/0004 , H01L21/84 , H01L27/24 , H01L29/785
摘要： A demultiplexer using transistors for accessing memory cell arrays. The demultiplexer includes (a) a substrate; (b) 2N semiconductor regions which are parallel to one another and run in a first direction; (c) first N gate electrode lines, which (i) run in a second direction which is perpendicular to the first direction, (ii) are electrically insulated from the 2N semiconductor regions, and (iii) are disposed between the first plurality of memory cells and the contact region; (d) a contact region; (e) a first plurality of memory cells. An intersection transistor exists at each of intersections between the first N gate electrode lines and the 2N semiconductor regions. In response to pre-specified voltage potentials being applied to the contact region and the first N gate electrode lines, memory cells of the first plurality of memory cells disposed on only one of the 2N semiconductor regions are selected.
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公开(公告)号：US20080203438A1
公开(公告)日：2008-08-28
申请号：US12114857
申请日：2008-05-05
IPC分类号： H01L27/10 , G11C17/08 , H01L21/8239
CPC分类号： H01L27/228 , G11C13/0004 , H01L21/84 , H01L27/24 , H01L29/785
摘要： A demultiplexer using transistors for accessing memory cell arrays. The demultiplexer includes (a) a substrate; (b) 2N semiconductor regions which are parallel to one another and run in a first direction; (c) first N gate electrode lines, which (i) run in a second direction which is perpendicular to the first direction, (ii) are electrically insulated from the 2N semiconductor regions, and (iii) are disposed between the first plurality of memory cells and the contact region; (d) a contact region; (e) a first plurality of memory cells. An intersection transistor exists at each of intersections between the first N gate electrode lines and the 2N semiconductor regions. In response to pre-specified voltage potentials being applied to the contact region and the first N gate electrode lines, memory cells of the first plurality of memory cells disposed on only one of the 2N semiconductor regions are selected.
摘要翻译： 一种使用晶体管访问存储单元阵列的解复用器。 解复用器包括（a）衬底; （b）彼此平行并在第一方向上延伸的N + N个半导体区域; （c）第一N栅电极线，其（i）沿与第一方向垂直的第二方向延伸，（ii）与二极管半导体区域电绝缘，以及（iii） 设置在所述第一多个存储单元和所述接触区域之间; （d）接触区域; （e）第一多个存储单元。 在第一N个栅极电极线和2个N个半导体区域之间的每个交叉处存在交叉晶体管。 响应于施加到接触区域和前N个栅电极线的预定电压电势，选择仅设置在2个N个半导体区域中的一个半导体区域上的第一多个存储单元的存储单元 。
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公开(公告)号：US08114723B2
公开(公告)日：2012-02-14
申请号：US12794826
申请日：2010-06-07
IPC分类号： H01L21/84
CPC分类号： H01L27/0207 , B82Y10/00 , H01L27/115 , H01L29/0665 , H01L29/0673 , H01L29/42336 , H01L29/785 , Y10S438/947 , Y10S977/888 , Y10S977/936
摘要： A structure, memory devices using the structure, and methods of fabricating the structure. The structure includes: an array of nano-fins, each nano-fin comprising an elongated block of semiconductor material extending axially along a first direction, the nano-fins arranged in groups of at least two nano-fins each, wherein ends of nano-fins of each adjacent group of nano-fins are staggered with respect to each other on both a first and a second side of the array; wherein nano-fins of each group of nano-fins are electrically connected to a common contact that is specific to each group of nano-fins such that the common contacts comprise a first common contact on the first side of the array and a second common contact on the second side of the array; and wherein each group of nano-fins has at least two gates that electrically control the conductance of nano-fins of the each group of nano-fins.
摘要翻译： 一种结构，使用该结构的存储器件以及该结构的制造方法。 该结构包括：纳米鳍片阵列，每个纳米鳍片包括沿着第一方向轴向延伸的细长的半导体材料块，所述纳米鳍片分别以至少两个纳米翅片的组排列，其中， 每个相邻组的纳米翅片的翅片在阵列的第一和第二侧上彼此交错; 其中每组纳米鳍片的纳米鳍片电连接到对于每组纳米鳍片特有的公共接触点，使得所述公共接触件包括在所述阵列的第一侧上的第一公共接触点和第二共同接触点 在阵列的第二面; 并且其中每组纳米鳍具有至少两个门，其电控制每组纳米鳍的纳米鳍的电导。
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公开(公告)号：US07829926B2
公开(公告)日：2010-11-09
申请号：US12114857
申请日：2008-05-05
IPC分类号： H01L27/108
CPC分类号： H01L27/228 , G11C13/0004 , H01L21/84 , H01L27/24 , H01L29/785
摘要： A demultiplexer using transistors for accessing memory cell arrays. The demultiplexer includes (a) a substrate; (b) 2N semiconductor regions which are parallel to one another and run in a first direction; (c) first N gate electrode lines, which (i) run in a second direction which is perpendicular to the first direction, (ii) are electrically insulated from the 2N semiconductor regions, and (iii) are disposed between the first plurality of memory cells and the contact region; (d) a contact region; (e) a first plurality of memory cells. An intersection transistor exists at each of intersections between the first N gate electrode lines and the 2N semiconductor regions. In response to pre-specified voltage potentials being applied to the contact region and the first N gate electrode lines, memory cells of the first plurality of memory cells disposed on only one of the 2N semiconductor regions are selected.
摘要翻译： 一种使用晶体管访问存储单元阵列的解复用器。 解复用器包括（a）衬底; （b）2N个彼此平行并沿第一方向延伸的半导体区域; （c）第一N栅电极线，其（i）沿与第一方向垂直的第二方向延伸，（ii）与2N个半导体区域电绝缘，并且（iii）设置在第一多个存储器 细胞和接触区域; （d）接触区域; （e）第一多个存储单元。 在第一N个栅电极线和2N个半导体区之间的交点处存在交叉晶体管。 响应于施加到接触区域和前N个栅电极线的预定电压电势，选择仅设置在2N个半导体区域中的一个上的第一多个存储单元的存储单元。
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公开(公告)号：US07393739B2
公开(公告)日：2008-07-01
申请号：US11468512
申请日：2006-08-30
IPC分类号： H01L21/8238
CPC分类号： H01L27/228 , G11C13/0004 , H01L21/84 , H01L27/24 , H01L29/785
摘要： A demultiplexer using transistors for accessing memory cell arrays. The demultiplexer includes (a) a substrate; (b) 2N semiconductor regions which are parallel to one another and run in a first direction; (c) first N gate electrode lines, which (i) run in a second direction which is perpendicular to the first direction, (ii) are electrically insulated from the 2N semiconductor regions, and (iii) are disposed between the first plurality of memory cells and the contact region; (d) a contact region; (e) a first plurality of memory cells. An intersection transistor exists at each of intersections between the first N gate electrode lines and the 2N semiconductor regions. In response to pre-specified voltage potentials being applied to the contact region and the first N gate electrode lines, memory cells of the first plurality of memory cells disposed on only one of the 2N semiconductor regions are selected.
摘要翻译： 一种使用晶体管访问存储单元阵列的解复用器。 解复用器包括（a）衬底; （b）彼此平行并在第一方向上延伸的N + N个半导体区域; （c）第一N栅电极线，其（i）沿与第一方向垂直的第二方向延伸，（ii）与二极管半导体区域电绝缘，以及（iii） 设置在所述第一多个存储单元和所述接触区域之间; （d）接触区域; （e）第一多个存储单元。 在第一N个栅极电极线和2个N个半导体区域之间的每个交叉处存在交叉晶体管。 响应于施加到接触区域和前N个栅电极线的预定电压电势，选择仅设置在2个N个半导体区域中的一个半导体区域上的第一多个存储单元的存储单元 。
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8.发明授权Decoding scheme for bipolar-based diode three-dimensional memory requiring unipolar programming 有权需要单极编程的双极型二极管三维存储器的解码方案公开(公告)号：US08842491B2
公开(公告)日：2014-09-23
申请号：US13551597
申请日：2012-07-17
IPC分类号： G11C8/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0023 , G11C13/0038 , G11C13/004 , G11C2213/71 , G11C2213/72
摘要： A system and method for operating a unipolar memory cell array including a bidirectional access diode. The system includes a column voltage switch electrically coupled to a plurality of column voltages. The column voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of column voltages includes at least one select column voltage and one deselect column voltage. The system includes a row voltage switch electrically coupled to a plurality of row voltages. The row voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of row voltages includes at least one select row voltage and one deselect row voltage. The system includes a column and row decoder electrically coupled to a select line of the column and row voltage switches, respectively.
摘要翻译： 一种用于操作包括双向存取二极管的单极存储单元阵列的系统和方法。 该系统包括电耦合到多个列电压的列电压开关。 列电压开关包括电耦合到双向存取二极管的输出。 多个列电压包括至少一个选择列电压和一个取消选择列电压。 该系统包括电耦合到多个行电压的行电压开关。 行电压开关包括电耦合到双向存取二极管的输出。 多个行电压包括至少一个选择行电压和一个取消选择行电压。 该系统包括分别电耦合到列的选择线和行电压开关的列和行解码器。
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公开(公告)号：US08811060B2
公开(公告)日：2014-08-19
申请号：US13485748
申请日：2012-05-31
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0004 , G11C13/003 , G11C17/165
摘要： A device for use with a memory cross-point array of elements, each of which comprises a selection device in series with a state-holding device, in one embodiment includes a controller, configured to apply at least one voltage and/or current pulse to a selected one or more of the elements, said selected one or more of the elements including a partially- or completely-shorted selection device, so that said partially- or completely-shorted selection device passes enough current so as to damage its corresponding state-holding device and place said corresponding state-holding device in a highly resistive state, while any other selection device that is not partially- or completely-shorted passes less current so that the state-holding device corresponding to said other selection device remains unaffected. Additional systems and methods are also presented.
摘要翻译： 一种与存储器交叉点阵列元件一起使用的装置，每个元件包括与状态保持装置串联的选择装置，在一个实施例中包括控制器，被配置为将至少一个电压和/或电流脉冲施加到 所选择的一个或多个元件，所述选定的一个或多个元件包括部分或完全短路的选择装置，使得所述部分或完全短路的选择装置通过足够的电流，以便损坏其对应的状态 - 并且将所述对应的状态保持装置置于高电阻状态，而没有部分或全部短路的任何其他选择装置通过较少电流，使得与所述其他选择装置对应的状态保持装置保持不受影响。 还介绍了其他系统和方法。
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10.发明授权Decoding scheme for bipolar-based diode three-dimensional memory requiring bipolar programming 失效需要双极性编程的双极型二极管三维存储器的解码方案公开(公告)号：US08755213B2
公开(公告)日：2014-06-17
申请号：US13407848
申请日：2012-02-29
CPC分类号： G11C13/0069 , G11C5/025 , G11C8/10 , G11C8/14 , G11C11/16 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0014 , G11C13/0023 , G11C2013/0071 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/77
摘要： A system and method for operating a bipolar memory cell array including a bidirectional access diode. The system includes a column voltage. The column voltage switch includes column voltages and an output electrically coupled to the bidirectional access diode. The column voltages include at least one write-one column voltage and at least one write-zero column voltage. The system also includes a row voltage switch. The row voltage switch includes row voltages and an output electrically coupled to the bidirectional access diode. The row voltages include at least one write-one row voltage and at least one write-zero row voltage. The system further includes a column decoder and a row decoder electrically coupled to a select line of the column voltage switch and row voltage switch, respectively. The system includes a write driver electrically coupled to the select lines of the row and column switches.
摘要翻译： 一种用于操作包括双向存取二极管的双极存储单元阵列的系统和方法。 该系统包括列电压。 列电压开关包括列电压和电耦合到双向存取二极管的输出。 列电压包括至少一个写一列电压和至少一个写零列电压。 该系统还包括行电压开关。 行电压开关包括行电压和电耦合到双向存取二极管的输出。 行电压包括至少一个写入一行电压和至少一个写入零行电压。 该系统还包括分别与列电压开关和行电压开关的选择线电耦合的列解码器和行解码器。 该系统包括电耦合到行和列开关的选择线的写入驱动器。
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