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70 条记录 (耗时 0.044 秒)

    Non-Volatile Memory With Flat Cell Structures And Air Gap Isolation
    43.
    发明申请
    Non-Volatile Memory With Flat Cell Structures And Air Gap Isolation 有权
    具有扁平单元结构和空气间隙隔离的非易失性存储器

    公开(公告)号：US20110309430A1

    公开(公告)日：2011-12-22

    申请号：US13162550

    申请日：2011-06-16

    申请人： Vinod Robert Purayath ,  George Matamis ,  Henry Chien ,  James Kai ,  Yuan Zhang

    发明人： Vinod Robert Purayath ,  George Matamis ,  Henry Chien ,  James Kai ,  Yuan Zhang

    IPC分类号： H01L29/788 ,  H01L21/764

    CPC分类号： H01L27/11524 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649

    摘要： High-density semiconductor memory is provided with enhancements to gate-coupling and electrical isolation between discrete devices in non-volatile memory. The intermediate dielectric between control gates and charge storage regions is varied in the row direction, with different dielectric constants for the varied materials to provide adequate inter-gate coupling while protecting from fringing fields and parasitic capacitances. Electrical isolation is further provided, at least in part, by air gaps that are formed in the column (bit line) direction and/or air gaps that are formed in the row (word line) direction.

    摘要翻译： 高密度半导体存储器提供了非易失性存储器中分立器件之间的栅极耦合和电隔离的增强。 控制栅极和电荷存储区域之间的中间电介质在行方向上变化，不同的介电常数用于不同的材料以提供足够的栅极间耦合，同时防止边缘场和寄生电容。 至少部分地通过在列（位线）方向上形成的气隙和/或在行（字线）方向上形成的气隙来进一步提供电隔离。

    Self aligned non-volatile memory cell and process for fabrication
    47.
    发明授权
    Self aligned non-volatile memory cell and process for fabrication 有权
    自对准非易失性存储单元和制造工艺

    公开(公告)号：US07105406B2

    公开(公告)日：2006-09-12

    申请号：US10600259

    申请日：2003-06-20

    申请人： Jeffrey Lutze ,  Tuan Pham ,  Henry Chien ,  George Matamis

    发明人： Jeffrey Lutze ,  Tuan Pham ,  Henry Chien ,  George Matamis

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825

    摘要： Floating gate structures are disclosed that have a projection that extends away from the surface of a substrate. This projection may provide the floating gate with increased surface area for coupling the floating gate and the control gate. In one embodiment, the word line extends downwards on each side of the floating gate to shield adjacent floating gates in the same string. In another embodiment, a process for fabricating floating gates with projections is disclosed. The projection may be formed so that it is self-aligned to the rest of the floating gate.

    摘要翻译： 公开了浮动栅极结构，其具有远离衬底的表面延伸的突起。 该突起可以为浮动栅极提供增加的表面积，用于耦合浮动栅极和控制栅极。 在一个实施例中，字线在浮动栅极的每一侧向下延伸以屏蔽相同串中的相邻浮动栅极。 在另一个实施例中，公开了一种用于制造具有突起的浮动栅极的工艺。 突起可以形成为使得其与浮动栅极的其余部分自对准。

    Non-volatile memory cells utilizing substrate trenches
    49.
    发明授权
    Non-volatile memory cells utilizing substrate trenches 有权

    公开(公告)号：US07087951B2

    公开(公告)日：2006-08-08

    申请号：US10848242

    申请日：2004-05-17

    申请人： Eliyahou Harari ,  Jack H. Yuan ,  George Samachisa ,  Henry Chien

    发明人： Eliyahou Harari ,  Jack H. Yuan ,  George Samachisa ,  Henry Chien

    IPC分类号： H01L29/76

    CPC分类号： H01L27/11521 ,  G11C16/0416 ,  H01L27/115 ,  H01L27/11553

    摘要： Several embodiments of flash EEPROM split-channel cell arrays are described that position the channels of cell select transistors along sidewalls of trenches in the substrate, thereby reducing the cell area. Select transistor gates are formed as part of the word lines and extend downward into the trenches with capacitive coupling between the trench sidewall channel portion and the select gate. In one embodiment, trenches are formed between every other floating gate along a row, the two trench sidewalls providing the select transistor channels for adjacent cells, and a common source/drain diffusion is positioned at the bottom of the trench. A third gate provides either erase or steering capabilities. In another embodiment, trenches are formed between every floating gate along a row, a source/drain diffusion extending along the bottom of the trench and upwards along one side with the opposite side of the trench being the select transistor channel for a cell. In another embodiment, select transistor gates of dual floating gate memory cells are extended into trenches or recesses in the substrate in order to lengthen the select transistor channel as the surface dimensions of the cell are being decreased. Techniques for manufacturing such flash EEPROM split-channel cell arrays are also included.

    Non-volatile memory cells utilizing substrate trenches
    50.
    发明授权
    Non-volatile memory cells utilizing substrate trenches 有权
    利用衬底沟槽的非易失性存储单元

    公开(公告)号：US06936887B2

    公开(公告)日：2005-08-30

    申请号：US09925134

    申请日：2001-08-08

    申请人： Eliyahou Harari ,  Jack H. Yuan ,  George Samachisa ,  Henry Chien

    发明人： Eliyahou Harari ,  Jack H. Yuan ,  George Samachisa ,  Henry Chien

    IPC分类号： H01L27/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11521 ,  G11C16/0416 ,  H01L27/115 ,  H01L27/11553

    摘要： Several embodiments of flash EEPROM split-channel cell arrays are described that position the channels of cell select transistors along sidewalls of trenches in the substrate, thereby reducing the cell area. Select transistor gates are formed as part of the word lines and extend downward into the trenches with capacitive coupling between the trench sidewall channel portion and the select gate. In one embodiment, trenches are formed between every other floating gate along a row, the two trench sidewalls providing the select transistor channels for adjacent cells, and a common source/drain diffusion is positioned at the bottom of the trench. A third gate provides either erase or steering capabilities. In another embodiment, trenches are formed between every floating gate along a row, a source/drain diffusion extending along the bottom of the trench and upwards along one side with the opposite side of the trench being the select transistor channel for a cell. In another embodiment, select transistor gates of dual floating gate memory cells are extended into trenches or recesses in the substrate in order to lengthen the select transistor channel as the surface dimensions of the cell are being decreased. Techniques for manufacturing such flash EEPROM split-channel cell arrays are also included.

    摘要翻译： 描述了闪存EEPROM分离通道单元阵列的几个实施例，其将单元选择晶体管的通道定位在衬底中的沟槽的侧壁，从而减小单元面积。 选择晶体管栅极形成为字线的一部分，并且通过沟槽侧壁沟道部分和选择栅极之间的电容耦合向下延伸到沟槽中。 在一个实施例中，在沿着一行的每隔一个浮置栅极之间形成沟槽，两个沟槽侧壁为相邻电池提供选择晶体管沟道，并且公共源极/漏极扩散部位于沟槽的底部。 第三个门提供擦除或转向功能。 在另一个实施例中，在沿着一排的每个浮置栅极之间形成沟槽，沿沟槽的底部延伸的源极/漏极扩散器和沿着一侧的向上并且沟槽的相对侧为用于电池的选择晶体管沟道。 在另一个实施例中，双浮置栅极存储器单元的选择晶体管栅极延伸到衬底中的沟槽或凹槽中，以便随着单元的表面尺寸减小而延长选择晶体管沟道。 还包括用于制造这种快速EEPROM分离通道单元阵列的技术。