公开(公告)号：US08541821B2

公开(公告)日：2013-09-24

申请号：US13234836

申请日：2011-09-16

申请人： Shubneesh Batra ,  Gurtej Sandhu

发明人： Shubneesh Batra ,  Gurtej Sandhu

IPC分类号： H01L21/336

CPC分类号： H01L21/28185 ,  B82Y10/00 ,  G11C16/0416 ,  G11C2216/06 ,  H01L21/28194 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66825 ,  H01L29/7883 ,  Y10S977/943

摘要： The invention provides a method of forming an electron memory storage device and the resulting device. The device comprises a gate structure which, in form, comprises a first gate insulating layer formed over a semiconductor substrate, a self-forming electron trapping layer of noble metal nano-crystals formed over the first gate insulating layer, a second gate insulating layer formed over the electron trapping layer, a gate electrode formed over the second gate insulating layer, and source and drain regions formed on opposite sides of the gate structure.

公开(公告)号：US20120028429A1

公开(公告)日：2012-02-02

申请号：US13234836

申请日：2011-09-16

申请人： Shubneesh Batra ,  Gurtej Sandhu

发明人： Shubneesh Batra ,  Gurtej Sandhu

IPC分类号： H01L21/336 ,  B82Y99/00

CPC分类号： H01L21/28185 ,  B82Y10/00 ,  G11C16/0416 ,  G11C2216/06 ,  H01L21/28194 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66825 ,  H01L29/7883 ,  Y10S977/943

摘要： The invention provides a method of forming an electron memory storage device and the resulting device. The device comprises a gate structure which, in form, comprises a first gate insulating layer formed over a semiconductor substrate, a self-forming electron trapping layer of noble metal nano-crystals formed over the first gate insulating layer, a second gate insulating layer formed over the electron trapping layer, a gate electrode formed over the second gate insulating layer, and source and drain regions formed on opposite sides of the gate structure.

摘要翻译： 本发明提供一种形成电子存储器存储装置的方法和所得到的装置。 该器件包括一个栅极结构，其形式包括形成在半导体衬底上的第一栅极绝缘层，形成在第一栅极绝缘层上的贵金属纳米晶体的自形成电子俘获层，形成的第二栅极绝缘层 形成在第二栅极绝缘层上方的栅极电极以及形成在栅极结构的相对侧上的源极和漏极区域。

公开(公告)号：US07160795B2

公开(公告)日：2007-01-09

申请号：US10293789

申请日：2002-11-12

申请人： Shubneesh Batra ,  Michael D. Chaine ,  Brent Keeth ,  Salman Akram ,  Troy A. Manning ,  Brian Johnson ,  Chris G. Martin ,  Todd A. Merritt ,  Eric J. Smith

发明人： Shubneesh Batra ,  Michael D. Chaine ,  Brent Keeth ,  Salman Akram ,  Troy A. Manning ,  Brian Johnson ,  Chris G. Martin ,  Todd A. Merritt ,  Eric J. Smith

IPC分类号： H01L21/44

CPC分类号： H01L24/05 ,  H01L23/5222 ,  H01L24/03 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01061 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105

摘要： A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels is described. The method comprises forming a bond pad at least partially exposed at the top surface of the integrated circuit, forming a metal pad on the metal level below the bond pad and forming an underlying metal pad on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads to the area of the bond pad is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.

摘要翻译： 描述了一种降低具有三个或更多个金属水平的集成电路中的寄生电容的方法。 该方法包括形成至少部分地暴露在集成电路的顶表面处的接合焊盘，在接合焊盘下方的金属层上形成金属焊盘，并在一个或多个下金属层的每一个上形成下面的金属焊盘。 在所示的实施例中，下面的金属焊盘中的至少一个的面积与焊盘的面积之比小于30％。 寄生电容因此大大降低，信号传播速度提高。

公开(公告)号：US20050029622A1

公开(公告)日：2005-02-10

申请号：US10931714

申请日：2004-09-01

申请人： Kenneth Marr ,  Shubneesh Batra

发明人： Kenneth Marr ,  Shubneesh Batra

IPC分类号： H01L23/525 ,  H01L29/00 ,  H01L21/44

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S257/928 ,  H01L2924/00

摘要： An antifuse structure and method of use are disclosed. According to one embodiment of the present invention a first programming voltage is coupled to a well of a first conductivity type in a substrate of a second conductivity type in an antifuse. A second programming voltage is coupled to a conductive terminal of the second conductivity type in the antifuse to create a current path through an insulator between the conductive terminal and the well to program the antifuse. The first programming voltage may be coupled to an ohmic contact in the well in the antifuse.

摘要翻译： 公开了反熔丝结构和使用方法。 根据本发明的一个实施例，第一编程电压在反熔丝中耦合到第二导电类型的衬底中的第一导电类型的阱。 第二编程电压在反熔丝中耦合到第二导电类型的导电端子，以产生通过导电端子和阱之间的绝缘体的电流路径，以对反熔丝进行编程。 第一编程电压可以耦合到反熔丝中的阱中的欧姆接触。

公开(公告)号：US06281104B1

公开(公告)日：2001-08-28

申请号：US09059663

申请日：1998-04-13

申请人： Shubneesh Batra ,  Gurtej Sandhu

发明人： Shubneesh Batra ,  Gurtej Sandhu

IPC分类号： H01L2144

CPC分类号： H01L23/53214 ,  H01L21/76877 ,  H01L21/76882 ,  H01L2924/0002 ,  H01L2924/00

摘要： Impurities are added to a conductor layer in a semiconductor process to prevent formation of void spaces and encourage complete filling of contacts. The impurities reduce the melting point and surface tension of a conductor layer, thereby improving filling characteristics during a reflow step. The impurities may be added at any time during the process, including during conductor deposition and/or reflow.

摘要翻译： 在半导体工艺中将杂质添加到导体层中以防止形成空隙并促进接触的完全填充。 杂质降低导体层的熔点和表面张力，从而改善回流步骤期间的填充特性。 杂质可以在该过程中的任何时间加入，包括在导体沉积和/或回流期间。

公开(公告)号：US6166398A

公开(公告)日：2000-12-26

申请号：US75433

申请日：1998-05-08

申请人： Shubneesh Batra ,  Monte Manning ,  Sanjay Banerjee ,  LeTien Jung

发明人： Shubneesh Batra ,  Monte Manning ,  Sanjay Banerjee ,  LeTien Jung

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/786 ,  H01L29/04

CPC分类号： H01L29/66757 ,  H01L21/28105 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78621

摘要： A method of forming a thin film transistor includes, a) forming a thin film transistor layer of semiconductive material; b) providing a gate operatively adjacent the thin film transistor layer; c) forming at least one electrically conductive sidewall spacer over at least one lateral edge of the gate, the spacer being electrically continuous therewith; and d) providing a source region, a drain region, a drain offset region, and a channel region in the thin film transistor layer; the drain offset region being positioned operatively adjacent the one electrically conductive sidewall spacer and being gated thereby. The spacer is formed by anisotropically etching a spacer forming layer.

摘要翻译： 形成薄膜晶体管的方法包括：a）形成半导体材料的薄膜晶体管层; b）提供可操作地邻近薄膜晶体管层的栅极; c）在所述栅极的至少一个侧边缘上形成至少一个导电侧壁间隔物，所述间隔件与其电连续; 以及d）在所述薄膜晶体管层中提供源极区，漏极区，漏极偏移区和沟道区; 所述漏极偏移区域可操作地邻近所述一个导电侧壁间隔物定位，并由此选通。 通过各向异性蚀刻间隔物形成层形成间隔物。

公开(公告)号：US6043117A

公开(公告)日：2000-03-28

申请号：US361692

申请日：1999-07-27

申请人： Shubneesh Batra ,  Monte Manning

发明人： Shubneesh Batra ,  Monte Manning

IPC分类号： H01L21/8244 ,  H01L27/06 ,  H01L27/11 ,  H01L21/8234

CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/1112 ,  Y10S257/903 ,  Y10S257/904 ,  Y10S438/918 ,  Y10S438/947

摘要： A method of forming an SRAM cell includes, a) providing a pair of pull-down gates having associated transistor diffusion regions operatively adjacent thereto, one of the diffusion regions of each pull-down gate being electrically connected to the other pull-down gate; b) providing a pair of pull-up resistor nodes for electrical connection with a pair of respective pull-up resistors, the pull-up nodes being in respective electrical connection with one of the pull-down gate diffusion regions and the other pull-down gate; c) providing a first electrical insulating layer outwardly of the resistor nodes; d) providing a pair of contact openings, with respective widths, through the first insulating layer to the pair of resistor nodes; e) providing a second electrical insulating layer over the first layer and to within the pair of contact openings to a thickness which is less than one-half the open widths; f) anisotropically etching the second electrical insulating layer to define respective electrical insulating annulus spacers received within the respective pair of contact openings and a pair of elongated pull-up resistor openings laterally inward thereof; g) providing electrically conductive material within the pair of elongated pull-up resistor openings in electrical connection with the pair of pull-up resistor nodes to define the pull-up resistors; and h) providing a Vcc line in electrical connection with the pull-up resistors. SRAM circuitry produced according to the above method and by other methods are also contemplated.

摘要翻译： 一种形成SRAM单元的方法包括：a）提供一对具有与其可操作相邻的相关联的晶体管扩散区的下拉栅极，每个下拉栅极的扩散区域之一电连接到另一个下拉栅极; b）提供一对上拉电阻器节点，用于与一对相应的上拉电阻器电连接，所述上拉节点与下拉栅极扩散区域中的一个和另一个下拉电阻器分别电连接 门; c）在所述电阻器节点之外提供第一电绝缘层; d）提供一对具有相应宽度的接触开口，穿过第一绝缘层到一对电阻器节点; e）在所述第一层之上和所述一对接触开口内设置第二电绝缘层，其厚度小于所述开口宽度的一半; f）各向异性蚀刻第二电绝缘层以限定容纳在相应的一对接触开口内的相应的电绝缘环形间隔件和一对横向向内的细长的上拉电阻器开口; g）在所述一对细长上拉电阻器开口内提供与所述一对上拉电阻器节点电连接的导电材料，以限定所述上拉电阻器; 和h）提供与上拉电阻器电连接的Vcc线。 还考虑了根据上述方法和其它方法生产的SRAM电路。

公开(公告)号：US6017782A

公开(公告)日：2000-01-25

申请号：US124939

申请日：1998-07-29

申请人： Shubneesh Batra ,  Monte Manning ,  Sanjay Banerjee ,  John Damiano, Jr.

发明人： Shubneesh Batra ,  Monte Manning ,  Sanjay Banerjee ,  John Damiano, Jr.

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/786 ,  H01L21/00

CPC分类号： H01L29/66757 ,  H01L21/26506 ,  H01L29/66765 ,  H01L29/78618 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/78675 ,  H01L29/78678 ,  H01L29/78681

摘要： A thin film transistor includes: a) a thin film transistor layer comprising a source region, a channel region and a drain region; the thin film transistor layer further comprising a drain offset region positioned between the drain region and the channel region; b) the channel region being substantially polycrystalline and having a first average crystalline grain size; and c) the drain offset region being substantially polycrystalline and having a second average crystalline grain size, the second average crystalline grain size being larger than the first average crystalline grain size. A method for forming such a construction using polycrystalline materials, preferably polysilicon, and an amorphizing silicon implant with subsequent recrystallization is also disclosed.

公开(公告)号：US6013543A

公开(公告)日：2000-01-11

申请号：US851464

申请日：1997-05-05

申请人： Monte Manning ,  Shubneesh Batra

发明人： Monte Manning ,  Shubneesh Batra

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/84

CPC分类号： H01L29/66757 ,  H01L29/66765 ,  H01L29/78624 ,  H01L29/78645 ,  H01L29/78648

摘要： A method of forming a thin film transistor of a first conductivity type includes, a) providing a thin film transistor layer of semiconductive material; b) first masking the thin film transistor layer to mask a desired drain offset region while leaving a desired channel region exposed; c) with the first masking in place, doping the exposed channel region with a conductivity enhancing impurity of a second type; d) second masking the thin film transistor layer to mask the channel region and the drain offset region and leave desired opposing source/drain regions exposed; and e) with the second masking in place, doping the exposed source/drain regions with a conductivity enhancing impurity of the first type. A thin film transistor includes, ii) a thin film layer of semiconductive material, the thin film layer comprising a source region, a drain region, a drain offset region and a channel region; the source and drain regions being conductively doped with a conductivity enhancing impurity of the first type to a concentration effective to render such source and drain regions electrically conductive; the channel region being doped with a conductivity enhancing impurity of a second type to a first concentration; the drain offset region being doped with a conductivity enhancing impurity of the second type to a second concentration, the second concentration being less than the first concentration; and ii) a gate positioned operatively adjacent the channel region. Alternately, the drain offset region consists essentially of undoped semiconductive material.

摘要翻译： 形成第一导电类型的薄膜晶体管的方法包括：a）提供半导体材料的薄膜晶体管层; b）首先掩蔽薄膜晶体管层以掩蔽期望的漏极偏移区域，同时留下期望的沟道区域暴露; c）在第一掩蔽位置的情况下，用暴露的沟道区掺杂导电增强杂质的第二类型; d）第二掩蔽薄膜晶体管层以掩蔽沟道区域和漏极偏移区域，并使期望的相对的源极/漏极区域暴露; 和e）在适当位置进行第二掩蔽，用暴露的源/漏区掺杂第一类型的电导率增强杂质。 薄膜晶体管包括：ii）半导体材料的薄膜层，所述薄膜层包括源极区，漏极区，漏极偏移区和沟道区; 源极和漏极区域被导电地掺杂有第一类型的导电性增强杂质，以使得有效地使得这种源极和漏极区域导电; 所述沟道区域掺杂有第二类型的导电性增强杂质至第一浓度; 所述漏极偏移区域掺杂有第二类型的电导率增强杂质至第二浓度，所述第二浓度小于所述第一浓度; 和ii）可操作地邻近通道区域定位的门。 或者，漏极偏移区域基本上由未掺杂的半导体材料组成。

公开(公告)号：US5953596A

公开(公告)日：1999-09-14

申请号：US769652

申请日：1996-12-19

申请人： Shubneesh Batra ,  Monte Manning ,  Sanjay Banerjee ,  LeTien Jung

发明人： Shubneesh Batra ,  Monte Manning ,  Sanjay Banerjee ,  LeTien Jung

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/786 ,  H01L21/00 ,  H01L21/84

CPC分类号： H01L29/66757 ,  H01L21/28105 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78621

摘要： A method of forming film transistor includes, a) forming a thin film transistor layer of semiconductive material; b) providing a gate operatively adjacent the thin film transistor layer; c) forming at least one electrically conductive sidewall spacer over at least one lateral edge of the gate, the spacer being electrically continuous therewith; and d) providing a source region, a drain region, a drain offset region, and a channel region in the thin film transistor layer; the drain offset region being positioned operatively adjacent the one electrically conductive sidewall spacer and being gated thereby. The spacer is formed by anisotropically etching a spacer forming layer.

摘要翻译： 一种形成薄膜晶体管的方法包括：a）形成半导体材料的薄膜晶体管层; b）提供可操作地邻近薄膜晶体管层的栅极; c）在所述栅极的至少一个侧边缘上形成至少一个导电侧壁间隔物，所述间隔件与其电连续; 以及d）在所述薄膜晶体管层中提供源极区，漏极区，漏极偏移区和沟道区; 所述漏极偏移区域可操作地邻近所述一个导电侧壁间隔物定位，并由此选通。 通过各向异性蚀刻间隔物形成层形成间隔物。