Non-volatile semiconductor memory having multiple external power supplies
    41.
    发明授权
    Non-volatile semiconductor memory having multiple external power supplies 有权
    具有多个外部电源的非易失性半导体存储器

    公开(公告)号:US08300471B2

    公开(公告)日:2012-10-30

    申请号:US13096874

    申请日:2011-04-28

    IPC分类号: G11C16/04

    摘要: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.

    摘要翻译: 存储器件包括诸如用于存储数据的闪存的核心存储器。 存储器件包括用于接收用于为闪速存储器供电的第一电压的第一电源输入。 另外,存储器件包括用于接收第二电压的第二电源输入。 存储器件包括被配置为接收第二电压并导出一个或多个内部电压的电源管理电路。 电源管理电路将内部电压提供或传送到闪存。 由功率管理电路(例如,电压转换器电路)产生并提供给核心存储器的不同的内部电压使得诸如针对核心存储器中的单元的读取/编程/擦除的操作。

    High bandwidth memory interface
    42.
    发明授权
    High bandwidth memory interface 有权
    高带宽存储器接口

    公开(公告)号:US08266372B2

    公开(公告)日:2012-09-11

    申请号:US11906756

    申请日:2007-10-03

    IPC分类号: G06F12/00

    摘要: A DRAM system configured for high bandwidth communication, the system includes at least one DRAM having resistive termination devices within the DRAM, and a controller connected to the DRAM through a data bus. The controller includes resistive termination devices and the data bus includes at least one clock line driven intermittently. The data bus provides write data from the controller to the DRAM, and provides read data from the DRAM to the controller.

    摘要翻译: 配置用于高带宽通信的DRAM系统,该系统包括至少一个DRAM,其具有DRAM内的电阻终端器件,以及通过数据总线连接到DRAM的控制器。 控制器包括电阻终端装置,数据总线包括间歇驱动的至少一个时钟线。 数据总线提供从控制器到DRAM的写入数据,并将数据从DRAM提供给控制器。

    High bandwidth memory interface
    43.
    发明授权
    High bandwidth memory interface 有权
    高带宽存储器接口

    公开(公告)号:US08250297B2

    公开(公告)日:2012-08-21

    申请号:US11978988

    申请日:2007-10-30

    IPC分类号: G06F12/00

    摘要: This invention describes an improved high bandwidth chip-to-chip interface for memory devices, which is capable of operating at higher speeds, while maintaining error free data transmission, consuming lower power, and supporting more load. Accordingly, the invention provides a memory subsystem comprising at least two semiconductor devices; a main bus containing a plurality of bus lines for carrying substantially all data and command information needed by the devices, the semiconductor devices including at least one memory device connected in parallel to the bus; the bus lines including respective row command lines and column command lines; a clock generator for coupling to a clock line, the devices including clock inputs for coupling to the clock line; and the devices including programmable delay elements coupled to the clock inputs to delay the clock edges for setting an input data sampling time of the memory device.

    摘要翻译: 本发明描述了一种用于存储器件的改进的高带宽芯片到芯片接口,其能够以更高的速度运行,同时保持无错误的数据传输,消耗较低的功率并支持更多的负载。 因此,本发明提供一种包括至少两个半导体器件的存储器子系统; 主总线,其包含用于承载所述设备所需的基本上所有数据和命令信息的多条总线,所述半导体器件包括与所述总线并联连接的至少一个存储器件; 总线包括各行命令行和列命令行; 用于耦合到时钟线的时钟发生器,所述器件包括用于耦合到时钟线的时钟输入; 并且所述设备包括耦合到所述时钟输入的可编程延迟元件,以延迟所述时钟边沿,以设置所述存储器件的输入数据采样时间。

    CONFIGURABLE MODULE AND MEMORY SUBSYSTEM
    44.
    发明申请
    CONFIGURABLE MODULE AND MEMORY SUBSYSTEM 有权
    可配置模块和存储器子系统

    公开(公告)号:US20100296256A1

    公开(公告)日:2010-11-25

    申请号:US12770376

    申请日:2010-04-29

    IPC分类号: H05K7/00

    摘要: A configurable memory subsystem includes a memory module with a circuit board having a first and a second memory-containing device (MCD) pair mounted thereto. Each MCD pair has a first MCD in communication with a second MCD. Each MCD has an input port, an output port, and a memory each communicating with a bridge. In response to a command, the bridge transfers at least one of a portion of a data packet from the input port to the output port or to the memory, or transfers a portion of a memory packet from the memory to the output port. A loop-back device receives the command and the data packet form the first MCD pair and transmits the command and data packet to the second MCD pair.

    摘要翻译: 可配置存储器子系统包括具有电路板的存储器模块,该电路板具有安装在其上的第一和第二存储器容纳装置(MCD)对。 每个MCD对具有与第二MCD通信的第一MCD。 每个MCD都有一个输入端口,一个输出端口和一个与桥连通的存储器。 响应于命令,桥将数据分组的一部分中的至少一个从输入端口传送到输出端口或存储器,或者将存储器分组的一部分从存储器传送到输出端口。 环回装置从第一MCD对接收命令和数据包,并将命令和数据包发送到第二MCD对。

    Apparatuses for synchronous transfer of information
    45.
    发明授权
    Apparatuses for synchronous transfer of information 有权
    用于信息同步传输的装置

    公开(公告)号:US07765376B2

    公开(公告)日:2010-07-27

    申请号:US11978896

    申请日:2007-10-30

    IPC分类号: G06F13/20

    摘要: Semiconductor devices provide for synchronous transfer of information through a data bus. Address, control and clock information is received, via a command bus and clock line, at a plurality of terminals, the command bus and clock line providing a source synchronous bus. A plurality of output drivers drive read data onto a plurality of terminals coupled to a data bus.

    摘要翻译: 半导体器件通过数据总线提供信息的同步传输。 通过命令总线和时钟线在多个终端处接收地址,控制和时钟信息,命令总线和时钟线提供源同步总线。 多个输出驱动器将读取的数据驱动到耦合到数据总线的多个终端上。

    Non-volatile semiconductor memory having multiple external power supplies
    46.
    发明授权
    Non-volatile semiconductor memory having multiple external power supplies 有权
    具有多个外部电源的非易失性半导体存储器

    公开(公告)号:US07639540B2

    公开(公告)日:2009-12-29

    申请号:US11955754

    申请日:2007-12-13

    IPC分类号: G11C16/00

    摘要: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.

    摘要翻译: 存储器件包括诸如用于存储数据的闪存的核心存储器。 存储器件包括用于接收用于为闪速存储器供电的第一电压的第一电源输入。 另外,存储器件包括用于接收第二电压的第二电源输入。 存储器件包括被配置为接收第二电压并导出一个或多个内部电压的电源管理电路。 电源管理电路将内部电压提供或传送到闪存。 由功率管理电路(例如,电压转换器电路)产生并提供给核心存储器的不同的内部电压使得诸如针对核心存储器中的单元的读取/编程/擦除的操作。

    Apparatuses for synchronous transfer of information
    47.
    发明申请
    Apparatuses for synchronous transfer of information 有权
    用于信息同步传输的装置

    公开(公告)号:US20080120457A1

    公开(公告)日:2008-05-22

    申请号:US11978896

    申请日:2007-10-30

    IPC分类号: G06F1/12 G06F12/00

    摘要: Semiconductor devices provide for synchronous transfer of information through a data bus. Address, control and clock information is received, via a command bus and clock line, at a plurality of terminals, the command bus and clock line providing a source synchronous bus. A plurality of output drivers drive read data onto a plurality of terminals coupled to a data bus.

    摘要翻译: 半导体器件通过数据总线提供信息的同步传输。 通过命令总线和时钟线在多个终端处接收地址,控制和时钟信息,命令总线和时钟线提供源同步总线。 多个输出驱动器将读取的数据驱动到耦合到数据总线的多个终端上。

    Synchronous memory read data capture
    48.
    发明申请
    Synchronous memory read data capture 有权
    同步存储器读取数据采集

    公开(公告)号:US20080005518A1

    公开(公告)日:2008-01-03

    申请号:US11477659

    申请日:2006-06-30

    IPC分类号: G06F13/00

    摘要: A method of snap-shot data training to determine the optimum timing of the DQS enable signal in a single read operation is provided. This is accomplished by first writing a Gray code count sequence into the memory and then reading it back in a single burst. The controller samples the read burst at a fixed interval from the time the command was issued to determine the loop-around delay. A simple truth table lookup determines the optimum DQS enable timing for normal reads. Advantageously, during normal read operations, the first positive edge of the enabled DQS signal is used to sample a counter that is enabled every time a command is issued. If the counter sample changes, indicating timing drift has occurred, the DQS enable signal can be adjusted to compensate for the drift and maintain a position centered in the DQS preamble. This technique can also be applied to a system that uses the iterative approach to determining DQS enable timing on power up. Another embodiment of the invention is a simple, low latency clock domain crossing circuit based on the DQS latched sample of the counter.

    摘要翻译: 提供了一种快照数据训练方法,用于在单次读取操作中确定DQS使能信号的最佳定时。 这是通过首先将格雷码计数序列写入存储器,然后在单个脉冲串中读回来完成的。 控制器从发出命令的时间开始以固定的时间间隔对读取脉冲串进行采样,以确定环路延迟。 简单的真值表查找确定正常读取的最佳DQS使能定时。 有利地,在正常读取操作期间,使能的DQS信号的第一上升沿用于对每次发出命令时启用的计数器进行采样。 如果计数器样本发生变化,则指示定时漂移已经发生,可以调整DQS使能信号以补偿漂移并保持以DQS前导码为中心的位置。 该技术也可以应用于使用迭代方法来确定上电时的DQS使能定时的系统。 本发明的另一个实施例是基于柜台的DQS锁存样本的简单的低延迟时钟域交叉电路。

    Compare circuit for a content addressable memory cell
    49.
    发明授权
    Compare circuit for a content addressable memory cell 失效
    内容可寻址存储单元的比较电路

    公开(公告)号:US07304876B2

    公开(公告)日:2007-12-04

    申请号:US11534873

    申请日:2006-09-25

    IPC分类号: G11C15/00

    CPC分类号: G11C15/04

    摘要: A ternary content addressable memory (CAM) cell is disclosed for providing reduced or minimized matchline (ML) capacitance and for increasing current between matchline and tail-line in the case of a mismatch. The speed of a CAM cell is generally inversely proportional to its ML capacitance, and proportional to the current. Conventional ternary CAM cells have many matchline transistors, each contributing to the matchline capacitance. Embodiments of the present invention have a single matchline transistor between a matchline and a ground line, or tail-line, of the CAM cell. The single matchline transistor couples the matchline to the tail-line in response to a discharge signal from a compare circuit. The compare circuit can be divided into a pull-up section for driving a gate voltage level control node and a discharge section for discharging the gate voltage level control node, the discharge signal being provided at the gate voltage level control node.

    摘要翻译: 公开了三元内容可寻址存储器(CAM)单元,用于在不匹配的情况下提供缩减或最小化匹配线(ML)电容并用于增加匹配线和尾线之间的电流。 CAM单元的速度通常与其ML电容成反比,并且与电流成比例。 传统的三元CAM单元具有许多匹配线晶体管,每个有助于匹配线电容。 本发明的实施例在CAM单元的匹配线和接地线或尾线之间具有单个匹配线晶体管。 单个匹配线晶体管响应于来自比较电路的放电信号将匹配线耦合到尾线。 比较电路可以分为用于驱动栅极电压电平控制节点的上拉部分和用于放电栅极电压电平控制节点的放电部分,放电信号被提供在栅极电压电平控制节点处。

    Matchline sense circuit and method
    50.
    发明授权
    Matchline sense circuit and method 有权
    匹配线检测电路和方法

    公开(公告)号:US07251148B2

    公开(公告)日:2007-07-31

    申请号:US11269659

    申请日:2005-11-09

    IPC分类号: G11C15/00 G11C7/00

    CPC分类号: G11C7/06 G11C15/04 G11C15/043

    摘要: A matchline sense circuit for detecting a rising voltage on a matchline of a CAM array is disclosed. The circuit initially precharges a matchline to ground before turning on a current source to supply current to the matchline and raise the voltage of the matchline. A reference matchline sense circuit generates a self-timed control signal to keep the current supply turned on for a predetermined duration of time. Sensed data on the matchlines are latched after the current source is turned off and the matchlines are precharged to ground. Because the matchline sense circuit of the present invention precharges the matchlines to ground instead of the supply voltage, VDD, less power is consumed. By sensing the rise of the matchline voltage to an n-channel transistor threshold potential, the matchline sensing operation speed is increased.

    摘要翻译: 公开了一种用于检测CAM阵列的匹配线上的上升电压的匹配线检测电路。 在开启电流源以将电流提供给匹配线之前,该电路首先将匹配线预先接地,并提高匹配线的电压。 参考匹配线检测电路产生自定时控制信号以保持电流供应在预定持续时间内接通。 电流源关闭后,匹配线上的感测数据将被锁存,并将匹配线预充电到地。 因为本发明的匹配线检测电路将匹配线预充电到地电而不是电源电压VDD,所以消耗较少的功率。 通过感测匹配线电压升高到n沟道晶体管阈值电位,匹配线感测操作速度增加。