公开(公告)号：US20140232464A1

公开(公告)日：2014-08-21

申请号：US13994672

申请日：2011-12-21

Applicant: Hongjiang Song

Inventor： Hongjiang Song

IPC: H03F3/45

CPC classification number: H03F3/45645 ,  H03F3/45179 ,  H03F2200/129 ,  H03F2203/45551 ,  H03F2203/45588 ,  H04L25/0276 ,  H04L27/0002 ,  H04L27/01

Abstract: Described herein is a low power high-speed digital receiver. The apparatus of the receiver comprises: a sampling unit operable to sample a differential input signal and to boost input signal gain, the sampling unit to generate a sampled differential signal with boosted input signal gain; and a differential amplifier to amplify the sampled differential signal with boosted input signal gain, the differential amplifier to generate a differential amplified signal.

Abstract translation: 这里描述的是低功率高速数字接收机。 接收机的装置包括：采样单元，可操作以对差分输入信号进行采样并提升输入信号增益，采样单元产生具有升压输入信号增益的采样差分信号; 和差分放大器，用升压的输入信号增益放大采样的差分信号，差分放大器产生差分放大信号。

公开(公告)号：US20140146932A1

公开(公告)日：2014-05-29

申请号：US13994627

申请日：2011-12-21

Applicant: Hongjiang Song

Inventor： Hongjiang Song

IPC: H04L7/00

CPC classification number: H04L7/033 ,  H03C3/00 ,  H03C2200/002 ,  H03H11/20 ,  H03H11/22 ,  H03H17/08 ,  H03H2007/0192 ,  H03K17/693 ,  H04L7/0029

Abstract: Described herein is an apparatus, method and system corresponding to relate to a low power digital phase interpolator (PI). The apparatus comprises: a digital mixer unit to generate phase signals from a series of input signals, the phase signals having phases which are digitally controlled; a poly-phase filter, coupled to the digital mixer unit, to generate a filtered signal by reducing phase error in the phase signals; and an output buffer, coupled to the poly-phase filter, to generate an output signal by buffering the filtered signal. The low power digital PI consumes less power compared to traditional current-mode PIs operating on the same power supply levels because the digital PI is independent of any bias circuit which are needed for current mode PIs.

Abstract translation: 这里描述了对应于低功率数字相位内插器（PI）的装置，方法和系统。 该装置包括：数字混合器单元，用于从一系列输入信号产生相位信号，相位信号具有数字控制的相位; 耦合到数字混频器单元的多相滤波器，通过减少相位信号中的相位误差来产生滤波信号; 以及耦合到多相滤波器的输出缓冲器，以通过缓冲滤波的信号来产生输出信号。 与传统的电流模式PI相比，低功耗数字PI功耗要低，因为数字PI独立于当前模式PI所需的任何偏置电路。

公开(公告)号：US07139544B2

公开(公告)日：2006-11-21

申请号：US10668638

申请日：2003-09-22

Applicant: Malcolm H Smith ,  Hongjiang Song

Inventor： Malcolm H Smith ,  Hongjiang Song

IPC: H04B1/10

CPC classification number: H04B1/30

Abstract: A direct-down conversion receiver may include a transconductance-capacitor (GmC) filter to filter undesirable mixing products and provide a filtered baseband-differential signal. The GmC filter may include first and second transconductance-capacitor (GmC) circuits in series and a transconductance-feedback circuit in feedback with the second transconductance-capacitor circuit. The GmC circuits may comprise cross-coupled pairs of transistors to receive a baseband-differential signal and generate a differential output current. The GmC circuits may also comprise MOSCAPs coupled respectively between the differential inputs of the GmC circuit and internal-feedback nodes. In some embodiments, a substantially-constant bias voltage may be maintained across the voltage-dependent capacitors to allow the voltage-dependent capacitors to provide a substantially constant capacitance.

Abstract translation: 直接降压转换接收器可以包括跨导电容（GmC）滤波器，以滤除不期望的混合产物并提供滤波的基带差分信号。 GmC滤波器可以包括串联的第一和第二跨导电容（GmC）电路和与第二跨导 - 电容电路反馈的跨导 - 反馈电路。 GmC电路可以包括交叉耦合的晶体管对以接收基带差分信号并产生差分输出电流。 GmC电路还可以包括分别耦合在GmC电路的差分输入和内部反馈节点之间的MOSCAP。 在一些实施例中，可以在电压相关的电容器两端保持基本上恒定的偏置电压，以允许电压相关的电容器提供基本恒定的电容。

公开(公告)号：US07042932B1

公开(公告)日：2006-05-09

申请号：US09473740

申请日：1999-12-28

Applicant: Hongjiang Song

Inventor： Hongjiang Song

IPC: H04B17/02 ,  H04L7/00 ,  H04L25/00

CPC classification number: H04J3/0602 ,  H04J3/0632

Abstract: A method includes receiving an indication of incoming data from a first serial bus and buffering the bits to accommodate a difference between a first rate of the incoming data and a second rate of outgoing data. During the buffering, the method includes detecting if at least some of the bits indicate a synchronization field.

Abstract translation: 一种方法包括从第一串行总线接收输入数据的指示并缓冲该比特以适应输入数据的第一速率与第二传出数据速率之间的差异。 在缓冲期间，该方法包括检测位中的至少一些是否指示同步字段。

公开(公告)号：US20060001490A1

公开(公告)日：2006-01-05

申请号：US10883358

申请日：2004-06-30

Applicant: Hongjiang Song

Inventor： Hongjiang Song

IPC: H03F3/45

CPC classification number: H03F3/4508 ,  H03F2203/45112 ,  H03F2203/45251 ,  H03F2203/45292 ,  H03F2203/45318 ,  H03F2203/45322 ,  H03F2203/45352 ,  H03F2203/45366

Abstract: A method and apparatus to provide a reconfigurable differential dual port current conveyor circuit are described.

Abstract translation: 描述了提供可重新配置的差分双端口电流输送电路的方法和装置。

公开(公告)号：US06917660B2

公开(公告)日：2005-07-12

申请号：US09873820

申请日：2001-06-04

Applicant: Hongjiang Song

Inventor： Hongjiang Song

IPC: G11C7/22 ,  H03K5/15 ,  H03L7/07 ,  H03L7/081 ,  H04L7/00 ,  H03D3/24

CPC classification number: H03L7/0805 ,  G11C7/22 ,  G11C7/222 ,  H03K5/15013 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0008 ,  H04L7/0037

Abstract: A signal delay circuit that compensates for other delays introduced within the signal delay circuit itself. A delay-locked loop may produce multiple delayed clock signals, each having a defined phase difference with respect to, and representing a different delay from, a reference clock. A synchronization circuit may determine a first selection value that selects a first delayed clock whose delay compensates for the propagation delays created in a selection circuit. A selection circuit may add a specified offset value to the first selection value to produce a second selection value, and use the second selection value to select a second delayed clock whose delay approximates the sum of the internal delay of the selection circuit and the delay specified by the offset value.

Abstract translation: 信号延迟电路，用于补偿信号延迟电路本身引入的其他延迟。 延迟锁定环路可以产生多个延迟时钟信号，每个延迟时钟信号相对于参考时钟具有定义的相位差并且表示与参考时钟不同的延迟。 同步电路可以确定选择其延迟补偿在选择电路中产生的传播延迟的第一延迟时钟的第一选择值。 选择电路可以将指定的偏移值添加到第一选择值以产生第二选择值，并且使用第二选择值来选择其延迟近似于选择电路的内部延迟和指定的延迟之和的第二延迟时钟 通过偏移值。

公开(公告)号：US20050064839A1

公开(公告)日：2005-03-24

申请号：US10668638

申请日：2003-09-22

Applicant: Malcolm Smith ,  Hongjiang Song

Inventor： Malcolm Smith ,  Hongjiang Song

IPC: H04B1/30 ,  H04B1/26

CPC classification number: H04B1/30

Abstract: A direct-down conversion receiver may include a transconductance-capacitor (GmC) filter to filter undesirable mixing products and provide a filtered baseband-differential signal. The GmC filter may include first and second transconductance-capacitor (GmC) circuits in series and a transconductance-feedback circuit in feedback with the second transconductance-capacitor circuit. The GmC circuits may comprise cross-coupled pairs of transistors to receive a baseband-differential signal and generate a differential output current. The GmC circuits may also comprise MOSCAPs coupled respectively between the differential inputs of the GmC circuit and internal-feedback nodes. In some embodiments, a substantially-constant bias voltage may be maintained across the voltage-dependent capacitors to allow the voltage-dependent capacitors to provide a substantially constant capacitance.

Abstract translation: 直接降压转换接收器可以包括跨导电容（GmC）滤波器，以滤除不期望的混合产物并提供滤波的基带差分信号。 GmC滤波器可以包括串联的第一和第二跨导电容（GmC）电路和与第二跨导 - 电容电路反馈的跨导 - 反馈电路。 GmC电路可以包括交叉耦合的晶体管对以接收基带差分信号并产生差分输出电流。 GmC电路还可以包括分别耦合在GmC电路的差分输入和内部反馈节点之间的MOSCAP。 在一些实施例中，可以在电压相关的电容器两端保持基本上恒定的偏置电压，以允许电压相关的电容器提供基本恒定的电容。

公开(公告)号：US06466615B1

公开(公告)日：2002-10-15

申请号：US09475486

申请日：1999-12-30

Applicant: Hongjiang Song

Inventor： Hongjiang Song

IPC: H03H740

CPC classification number: H03H17/04 ,  H04L25/03006

Abstract: An apparatus including a plurality of quantizers each configured to compare a selected threshold signal with an input signal and generate an output, a multiplexer, coupled to the plurality of quantizers, that selects one of the plurality of quantizer outputs according to a frequency response, and a multiplication-accumulation (MAC) unit, coupled to the multiplexer, the MAC to generate an output based on a previously selected one of the quantizer outputs according to the frequency response.

Abstract translation: 一种包括多个量化器的装置，每个量化器被配置为将所选择的阈值信号与输入信号进行比较，并产生耦合到多个量化器的输出，多路复用器，其根据频率响应选择多个量化器输出中的一个;以及 耦合到所述多路复用器的乘法累积（MAC）单元，所述MAC基于根据所述频率响应的先前选择的一个量化器输出来产生输出。