公开(公告)号：US20240337692A1

公开(公告)日：2024-10-10

申请号：US18746853

申请日：2024-06-18

Applicant: Intel Corporation

Inventor： Rajiv Kumar ,  Amit Agarwal ,  Steven Hsu ,  Scott Weber

IPC: G01R31/3185

CPC classification number: G01R31/318541 ,  G01R31/318572

Abstract: A flip-flop circuit includes first and second storage circuits. The flip-flop circuit is configurable to store first values of a data signal in the first storage circuit in response to rising edges of a clock signal and to store second values of the data signal in the second storage circuit in response to falling edges of the clock signal during a double edge triggered mode. The flip-flop circuit is configurable to store third values of the data signal in the first storage circuit and to output the third values from the first storage circuit in response to the clock signal during a single edge triggered mode.

公开(公告)号：US20230376274A1

公开(公告)日：2023-11-23

申请号：US18362529

申请日：2023-07-31

Applicant: Intel Corporation

Inventor： Mark Anders ,  Arnab Raha ,  Amit Agarwal ,  Steven Hsu ,  Deepak Abraham Mathaikutty ,  Ram K. Krishnamurthy ,  Martin Power

IPC: G06F7/544 ,  G06F7/487 ,  G06F7/485 ,  G06F5/01

CPC classification number: G06F7/5443 ,  G06F7/4876 ,  G06F7/485 ,  G06F5/012

Abstract: A fused dot-product multiply-accumulate (MAC) circuit may support variable precisions of floating-point data elements to perform computations (e.g., MAC operations) in deep learning operations. An operation mode of the circuit may be selected based on the precision of an input element. The operation mode may be a FP16 mode or a FP8 mode. In the FP8 mode, product exponents may be computed based on exponents of floating-point input elements. A maximum exponent may be selected from the one or more product exponents. A global maximum exponent may be selected from a plurality of maximum exponents. A product mantissa may be computed and aligned with another product mantissa based on a difference between the global maximum exponent and a corresponding maximum exponent. An adder tree may accumulate the aligned product mantissas and compute a partial sum mantissa. The partial sum mantissa may be normalized using the global maximum exponent.

公开(公告)号：US11442103B2

公开(公告)日：2022-09-13

申请号：US17240877

申请日：2021-04-26

Applicant: Intel Corporation

Inventor： Amit Agarwal ,  Ram Krishnamurthy ,  Satish Damaraju ,  Steven Hsu ,  Simeon Realov

IPC: G01R31/317 ,  G01R31/3177 ,  H03K3/037 ,  G01R31/3185

Abstract: An apparatus is provided which comprises: a multi-bit quad latch with an internally coupled level sensitive scan circuitry; and a combinational logic coupled to an output of the multi-bit quad latch. Another apparatus is provided which comprises: a plurality of sequential logic circuitries; and a clocking circuitry comprising inverters, wherein the clocking circuitry is shared by the plurality of sequential logic circuitries.

公开(公告)号：US20220224316A1

公开(公告)日：2022-07-14

申请号：US17711638

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Amit Agarwal ,  Steven Hsu ,  Simeon Realov ,  Mahesh Kumashikar ,  Ram Krishnamurthy

IPC: H03K3/037 ,  G01R31/3177 ,  H03K3/038 ,  H03K19/20

Abstract: A fast Mux-D scan flip-flop is provided, which bypasses a scan multiplexer to a master keeper side path, removing delay overhead of a traditional Mux-D scan topology. The design is compatible with simple scan methodology of Mux-D scan, while preserving smaller area and small number of inputs/outputs. Since scan Mux is not in the forward critical path, circuit topology has similar high performance as level-sensitive scan flip-flop and can be easily converted into bare pass-gate version. The new fast Mux-D scan flip-flop combines the advantages of the conventional LSSD and Mux-D scan flip-flop, without the disadvantages of each.

公开(公告)号：US20190280693A1

公开(公告)日：2019-09-12

申请号：US16335092

申请日：2017-08-30

Applicant: Intel Corporation

Inventor： Steven K. Hsu ,  Amit Agarwal ,  Ram K. Krishnamurthy

IPC: H03K19/0185 ,  H03K3/037

Abstract: Some embodiments include apparatus and methods using an input stage and an output stage of a circuit. The input stage operates to receive an input signal and a clock signal and to provide an internal signal at an internal node based at least in part on the input signal. The input signal has levels in a first voltage range. The internal signal has levels in a second voltage range greater than the first voltage range. The output stage operates to receive the internal signal, the clock signal, and an additional signal generated based on the input signal. The output stage provides an output signal based at least in part on the input signal and the additional signal. The output signal has a third voltage range greater than the first voltage range.

公开(公告)号：US20190187208A1

公开(公告)日：2019-06-20

申请号：US15846047

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Amit Agarwal ,  Ram Krishnamurthy ,  Satish Damaraju ,  Steven Hsu ,  Simeon Realov

IPC: G01R31/317 ,  H03K3/037 ,  G01R31/3177

Abstract: An apparatus is provided which comprises: a multi-bit quad latch with an internally coupled level sensitive scan circuitry; and a combinational logic coupled to an output of the multi-bit quad latch. Another apparatus is provided which comprises: a plurality of sequential logic circuitries; and a clocking circuitry comprising inverters, wherein the clocking circuitry is shared by the plurality of sequential logic circuitries.

公开(公告)号：US10177765B2

公开(公告)日：2019-01-08

申请号：US15244839

申请日：2016-08-23

Applicant: Intel Corporation

Inventor： Steven K. Hsu ,  Amit Agarwal ,  Iqbal R. Rajwani ,  Simeon Realov ,  Ram K. Krishnamurthy

IPC: H03K19/00 ,  H03K19/0944 ,  H03K19/20

Abstract: An apparatus is provided which comprises: a clock node; a test node; an enable node; and an AND-OR-INVERT (AOI) static latch coupled to the clock node, test node, and enable node, wherein the AOI static latch has embedded NOR functionality. Another apparatus comprises: a critical timing path having a pass-gate based integrated clock gate; and a non-critical timing path electrically coupled to the critical timing path, wherein the non-critical timing path includes an AND-OR-Inverter (AOI) based integrated clock gate with embedded NOR functionality.

公开(公告)号：US20180145663A1

公开(公告)日：2018-05-24

申请号：US15860562

申请日：2018-01-02

Applicant: INTEL CORPORATION

Inventor： Amit Agarwal ,  Steven K. Hsu ,  Simeon Realov ,  Iqbal R. Rajwani ,  Ram K. Krishnamurthy

IPC: H03K3/3562 ,  H03K3/037

CPC classification number: H03K3/3562 ,  H03K3/0372 ,  H03K3/35625

Abstract: An apparatus is provided which comprises: a clock node; a first inverter having an input coupled to the clock node; a data node; a master latch with a shared p-type keeper coupled to an output of the first inverter, the master latch coupled to the data node; and a slave latch coupled to an output of the master latch, the slave latch having a shared p-type keeper and a shared n-type footer, wherein the shared p-type keeper and the shared n-type footer of the slave latch are coupled to the clock node and the input of the first inverter.

公开(公告)号：US20180091150A1

公开(公告)日：2018-03-29

申请号：US15277189

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Steven K. Hsu ,  Amit Agarwal ,  Ram K. Krishnamurthy

IPC: H03K19/0185 ,  H03K3/037

CPC classification number: H03K19/018521 ,  H03K3/037 ,  H03K3/0372

Abstract: Some embodiments include apparatus and methods using an input stage and an output stage of a circuit. The input stage operates to receive an input signal and a clock signal and to provide an internal signal at an internal node based at least in part on the input signal. The input signal has levels in a first voltage range. The internal signal has levels in a second voltage range greater than the first voltage range. The output stage operates to receive the internal signal, the clock signal, and an additional signal generated based on the input signal. The output stage provides an output signal based at least in part on the input signal and the additional signal. The output signal has a third voltage range greater than the first voltage range.

公开(公告)号：US20180069538A1

公开(公告)日：2018-03-08

申请号：US15260180

申请日：2016-09-08

Applicant: Intel Corporation

Inventor： Amit Agarwal ,  Steven K. Hsu ,  Ram K. Krishnamurthy

IPC: H03K3/356 ,  H03K3/012

CPC classification number: H03K3/012 ,  H03K3/35625

Abstract: An apparatus is provided which comprises a clock inverter having an input coupled to a clock node, the clock inverter having an output, wherein the clock inverter has an N-well which is coupled to a first power supply; and a plurality of sequential logics coupled to the output of the clock inverter and also coupled to the clock node, wherein at least one sequential logics of the plurality of the sequential logics has an N-well which is coupled to a second power supply, wherein the second power supply has a voltage level lower than a voltage level of the first power supply.