公开(公告)号：US20230091205A1

公开(公告)日：2023-03-23

申请号：US17479582

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Adrian Moga ,  Ugonna Echeruo ,  Eduard Roytman ,  Krishnakanth Sistla ,  Joseph Nuzman ,  Brinda Ganesh ,  Meenakshisundaram Chinthamani ,  Yen-Cheng Liu ,  Sai Prashanth Muralidhara ,  Vivek Kozhikkottu ,  Hanna Alam ,  Narasimha Sridhar Srirangam

IPC: G06F12/0862 ,  G06F13/28

Abstract: Methods and apparatus relating to memory side prefetch architecture for improved memory bandwidth are described. In an embodiment, logic circuitry transmits a Direct Memory Controller Prefetch (DMCP) request to cause a prefetch of data from memory. A memory controller receives the DMCP request and issues a plurality of read operations to the memory in response to the DMCP request. Data read from the memory is stored in a storage structure in response to the plurality of read operations. Other embodiments are also disclosed and claimed.

公开(公告)号：US20220335126A1

公开(公告)日：2022-10-20

申请号：US17590470

申请日：2022-02-01

Applicant: Intel Corporation

Inventor： Robert S. Chappell ,  Jared W. Stark, IV ,  Joseph Nuzman ,  Stephen Robinson ,  Jason W. Brandt

IPC: G06F21/55 ,  G06F21/62 ,  G06F9/48 ,  G06F12/0802 ,  G06F9/30

Abstract: Systems, methods, and apparatuses relating to microarchitectural mechanisms for the prevention of side-channel attacks are disclosed herein. In one embodiment, a processor includes a core having a plurality of physical contexts to execute a plurality of threads, a plurality of structures shared by the plurality of threads, a context mapping structure to map context signatures to respective physical contexts of the plurality of physical contexts, each physical context to identify and differentiate state of the plurality of structures, and a context manager circuit to, when one or more of a plurality of fields that comprise a context signature is changed, search the context mapping structure for a match to another context signature, and when the match is found, a physical context associated with the match is set as an active physical context for the core.

公开(公告)号：US11416281B2

公开(公告)日：2022-08-16

申请号：US16474978

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  Gilbert Neiger ,  Narayan Ranganathan ,  Stephen R. Van Doren ,  Joseph Nuzman ,  Niall D. McDonnell ,  Michael A. O'Hanlon ,  Lokpraveen B. Mosur ,  Tracy Garrett Drysdale ,  Eriko Nurvitadhi ,  Asit K. Mishra ,  Ganesh Venkatesh ,  Deborah T. Marr ,  Nicholas P. Carter ,  Jonathan D. Pearce ,  Edward T. Grochowski ,  Richard J. Greco ,  Robert Valentine ,  Jesus Corbal ,  Thomas D. Fletcher ,  Dennis R. Bradford ,  Dwight P. Manley ,  Mark J. Charney ,  Jeffrey J. Cook ,  Paul Caprioli ,  Koichi Yamada ,  Kent D. Glossop ,  David B. Sheffield

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

公开(公告)号：US20220207138A1

公开(公告)日：2022-06-30

申请号：US17134350

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Carlos Rozas ,  Fangfei Liu ,  Xiang Zou ,  Francis McKeen ,  Jason W. Brandt ,  Joseph Nuzman ,  Alaa Alameldeen ,  Abhishek Basak ,  Scott Constable ,  Thomas Unterluggauer ,  Asit Mallick ,  Matthew Fernandez

IPC: G06F21/55 ,  G06F21/54 ,  G06F9/30 ,  G06F9/38

Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes a decode circuitry and store circuitry coupled to the decode circuitry. The decode circuitry is to decode a store hardening instruction to mitigate vulnerability to a speculative execution attack. The store circuitry is to be hardened in response to the store hardening instruction.

公开(公告)号：US20220197797A1

公开(公告)日：2022-06-23

申请号：US17130676

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Ayan Mandal ,  Leon Polishuk ,  Oz Shitrit ,  Joseph Nuzman

IPC: G06F12/0811 ,  G06F12/128 ,  G06F12/0815

Abstract: An embodiment of an integrated circuit may comprise a core, and a cache controller coupled to the core, the cache controller including circuitry to identify data from a working set for dynamic inclusion in a next level cache based on an amount of re-use of the next level cache, send a shared copy of the identified data to a requesting core of one or more processor cores, and maintain a copy of the identified data in the next level cache. Other embodiments are disclosed and claimed.

公开(公告)号：US11249909B2

公开(公告)日：2022-02-15

申请号：US16235276

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Hanna Alam ,  Joseph Nuzman

IPC: G06F12/00 ,  G06F12/0862 ,  G06F12/0877 ,  G06F12/0897

Abstract: Systems and methods to predict and prefetch a cache access based on a delta pattern are disclosed. The delta pattern may comprise a sequence of differences between first and second cache accesses within a page. In one example, a processor includes execution circuitry to extract a delta history corresponding to a delta pattern associated with one or more previous cache accesses corresponding to a page of memory. The processor execution circuitry further generates a bucketed delta history based on the delta history corresponding to the page of memory and selects a prediction entry based on the bucketed delta history. The processor execution circuitry then identifies one or more prefetch candidates based on a confidence threshold, with the confidence threshold indicating one or more probable delta patterns, and filters the one or more prefetch candidates. Prefetch circuitry of the processor then predicts and prefetches a cache access based the one or more prefetch candidates.

公开(公告)号：US20220012059A1

公开(公告)日：2022-01-13

申请号：US17341068

申请日：2021-06-07

Applicant: Intel Corporation

Inventor： Ravi Sahita ,  Deepak Gupta ,  Vedvyas Shanbhogue ,  David Hansen ,  Jason W. Brandt ,  Joseph Nuzman ,  Mingwei Zhang

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/14

Abstract: Systems, methods, and apparatuses relating to instructions to compartmentalize memory accesses and execution (e.g., non-speculative and speculative) are described. In one embodiment, a compartment manager circuit is to determine, when a compartment control register of a hardware processor core is set to an enable value, that a first subset of code requested for execution on the hardware processor core in user privilege is within a first compartment of memory, load a first compartment descriptor for the first compartment into one or more registers of the hardware processor core from the memory, check if the first compartment is marked in the first compartment descriptor, within the one or more registers of the hardware processor core, as a management compartment, and, when the first compartment is marked in the first compartment descriptor as the management compartment, allowing the first subset of the code within the first compartment to load a second compartment descriptor for a second compartment of the memory into the one or more registers of the hardware processor core from the memory, switching execution from the first subset of code within the first compartment to a second subset of code in user privilege within the second compartment, allowing speculative memory accesses for the second subset of code only within the second compartment, and preventing a memory access outside of the second compartment for the second subset of code as indicated by the second compartment descriptor stored within the one or more registers of the hardware processor core.

公开(公告)号：US11036501B2

公开(公告)日：2021-06-15

申请号：US16231580

申请日：2018-12-23

Applicant: Intel Corporation

Inventor： Raanan Sade ,  Joseph Nuzman ,  Hubert Nueckel

IPC: G06F9/30 ,  G06F9/52

Abstract: An apparatus and method for executing an atomic test and update instruction. For example, one embodiment of a processor comprises: a decoder to decode an atomic test and update (ATU) instruction having a first operand specifying a first value in a first storage location, a second operand specifying a second value in a second storage location, a third operand specifying a third value in a third storage location, and an opcode specifying a condition to be tested relative to the first and second values; and execution circuitry to perform a load lock operation to load the first value from the first storage location, the load lock operation to prevent access by another instruction before a result of the ATU instruction is stored, the execution circuitry to test a condition related the first value and the second value, wherein if the condition is met then the execution circuitry is to add the first value and the third value to generate a sum and to store the sum to the first storage location.

公开(公告)号：US11029957B1

公开(公告)日：2021-06-08

申请号：US16833478

申请日：2020-03-27

Applicant: INTEL CORPORATION

Inventor： Ravi Sahita ,  Deepak Gupta ,  Vedvyas Shanbhogue ,  David Hansen ,  Jason W. Brandt ,  Joseph Nuzman ,  Mingwei Zhang

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/14

Abstract: Systems, methods, and apparatuses relating to instructions to compartmentalize memory accesses and execution (e.g., non-speculative and speculative) are described. In one embodiment, a compartment manager circuit is to determine, when a compartment control register of a hardware processor core is set to an enable value, that a first subset of code requested for execution on the hardware processor core in user privilege is within a first compartment of memory, load a first compartment descriptor for the first compartment into one or more registers of the hardware processor core from the memory, check if the first compartment is marked in the first compartment descriptor, within the one or more registers of the hardware processor core, as a management compartment, and, when the first compartment is marked in the first compartment descriptor as the management compartment, allowing the first subset of the code within the first compartment to load a second compartment descriptor for a second compartment of the memory into the one or more registers of the hardware processor core from the memory, switching execution from the first subset of code within the first compartment to a second subset of code in user privilege within the second compartment, allowing speculative memory accesses for the second subset of code only within the second compartment, and preventing a memory access outside of the second compartment for the second subset of code as indicated by the second compartment descriptor stored within the one or more registers of the hardware processor core.

公开(公告)号：US11023382B2

公开(公告)日：2021-06-01

申请号：US15853640

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Raanan Sade ,  Jason Brandt ,  Mark J. Charney ,  Joseph Nuzman ,  Leena Puthiyedath ,  Rinat Rappoport ,  Vivekananthan Sanjeepan ,  Robert Valentine

IPC: G06F12/0877 ,  G06F12/0846 ,  G06F12/0895 ,  G06F12/0813 ,  G06F12/0804 ,  G06F12/0875 ,  G06F12/02 ,  G06F9/30 ,  G06T1/60

Abstract: Implementations of using tiles for caching are detailed In some implementations, an instruction execution circuitry executes one or more instructions, a register state cache coupled to the instruction execution circuitry holds thread register state in a plurality of registers, and backing storage pointer storage stores a backing storage pointer, wherein the backing storage pointer is to reference a state backing storage area in external memory to store the thread register state stored in the register state cache.