公开(公告)号：US20210144844A1

公开(公告)日：2021-05-13

申请号：US17154551

申请日：2021-01-21

Applicant: Intel Corporation

Inventor： Jaejin Lee ,  Min Suet Lim ,  Luis Paniagua Acuna ,  Tin Poay Chuah

IPC: H05K1/02 ,  H05K1/11

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to a shielding layer to be inserted under an inductor footprint to mitigate the impact of electromagnetic interference (EMI) onto electrical traces beneath the shielding layer and under the inductor footprint. In embodiments, the electrical traces may be high-speed input/output (HSIO) traces that may be particularly susceptible to data corruption given the level of EMI. In embodiments, the shielding layer may be a high density metallization shield within dielectric stack-up layers. In embodiments, these layers may use unique via patterns or shaped metal preform shields to enable routing under an inductor at a higher layer of the PCB. Other embodiments may be described and/or claimed.

公开(公告)号：US20210035880A1

公开(公告)日：2021-02-04

申请号：US16306884

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim ,  Xi Guo

IPC: H01L23/367 ,  H01L23/498 ,  H01L25/065 ,  H01L21/48

Abstract: Electronic device package on package (POP) technology is disclosed. A POP can comprise a first electronic device package including a heat source. The POP can also comprise a second electronic device package disposed on the first electronic device package. The second electronic device package can include a substrate having a heat transfer portion proximate the heat source that facilitates heat transfer from the heat source through a thickness of the substrate. The substrate can also have an electronic component portion at least partially about the heat transfer portion that facilitates electrical communication. In addition, the POP can comprise an electronic component operably coupled to the electronic component portion.

公开(公告)号：US20200325711A1

公开(公告)日：2020-10-15

申请号：US16859452

申请日：2020-04-27

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Howe Yin Loo ,  Min Suet Lim ,  Jackson Chung Peng Kong ,  Poh Tat Oh

IPC: E05D3/06 ,  G06F1/16 ,  G06F1/3218 ,  G06F1/3234 ,  E05D11/00 ,  H05K5/02

Abstract: Particular embodiments described herein provide for an electronic device, such as a notebook computer or laptop, which includes a circuit board coupled to a plurality of electronic components (which includes any type of components, elements, circuitry, etc.). One particular example implementation of the electronic device may include a low profile hinge design that includes a micro-hinge. The micro-hinge can couple a first element to a second element and can include a first attachment that couples to the first element, a second attachment that couples to the second element, and a plurality of linkages that couples the first attachment to the second attachment. The low profile hinge can further include a plurality of micro-hinges and a plurality of support rods.

公开(公告)号：US20200083157A1

公开(公告)日：2020-03-12

申请号：US16469100

申请日：2017-11-29

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Min Suet Lim ,  J-Wing Teh ,  Bok Eng Cheah

IPC: H01L23/525 ,  H01L23/48 ,  H01L25/00 ,  H01L23/00 ,  H01L27/02

Abstract: A device and method of utilizing a programmable redistribution die to redistribute the outputs of semiconductor dies. Integrated circuit packages using a programmable redistribution die are shown. Methods of creating a programmable redistribution die are shown.

公开(公告)号：US20200027639A1

公开(公告)日：2020-01-23

申请号：US16402467

申请日：2019-05-03

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim ,  Chin Lee Kuan ,  Siew Fong Yap

IPC: H01F27/02 ,  G05F1/56

Abstract: An electronic device comprises an air core inductor including an electronic semiconductor package including a first portion of the air core inductor internal to the electronic semiconductor package; and an electrically conductive layer arranged on a first external surface of the electronic semiconductor package and electrically connected as a second portion of the air core inductor.

公开(公告)号：US10319698B2

公开(公告)日：2019-06-11

申请号：US15354291

申请日：2016-11-17

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Min Suet Lim ,  Jackson Chung Peng Kong

IPC: H01L25/065 ,  H01L23/538 ,  H01L25/00 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498

Abstract: A microelectronic device package including multiple layers of stacked die. Multiple die layers in the package can include two or more die. At least two die in a first layer will be laterally spaced from one another to define a first gap extending in a first direction; and at least two die in a second layer will be laterally spaced from one another to define a second gap extending in a second direction that is angularly offset from the first direction. The first and second directions can be perpendicular to one another.

公开(公告)号：US10256519B2

公开(公告)日：2019-04-09

申请号：US15396181

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Wil Choon Song ,  Khang Choong Yong ,  Min Suet Lim ,  Eng Huat Goh ,  Boon Ping Koh

IPC: H01P3/08 ,  H05K1/02 ,  H01P11/00 ,  H01P3/02 ,  H01P3/10 ,  H01P5/12

Abstract: Various embodiments disclosed relate to a circuit. The circuit includes a transceiver adapted to generate a signal. A stranded transmission line is connected to the transceiver. The signal is then transmitted through the first pair of conductive strands.

公开(公告)号：US20190103358A1

公开(公告)日：2019-04-04

申请号：US15845336

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Min Suet Lim ,  Chee Kheong Yoon ,  Jia Yan Go

IPC: H01L23/538 ,  H05K1/18 ,  H01L25/18 ,  H01L25/00

Abstract: An electronic device may be a first package. The first package may include a first substrate having a first mounting surface. A first die may be coupled to the first mounting surface. A first interconnect region may be laterally spaced from the first die. The first package may be interconnected with a second package. The second package may include a second die coupled to a second mounting surface. Interconnection of the first package with the second package may establish one or more electrical communication pathways between the first package and the second package. The interconnection of the first package with the second package may interconnect the first die with the second die such that the first die and second die are in communication only through the one or more electrical communication pathways.

公开(公告)号：US20190103346A1

公开(公告)日：2019-04-04

申请号：US15845531

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Min Suet Lim ,  Jiun Hann Sir ,  Hoay Tien Teoh ,  Jimmy Huat Since Huang

IPC: H01L23/498 ,  H05K1/18 ,  H01L21/56 ,  H01L23/538 ,  H01L23/522 ,  H01L23/00

Abstract: An electronic package with passive components located between a first substrate and a second substrate. The electronic package can include a first substrate including a device interface for communication with an electronic device. An interposer can be electrically coupled to the first substrate. A second substrate can be offset from the first substrate at a distance. The second substrate can be electrically coupled to the first substrate through the interposer. A passive component can be attached to one of the first substrate or the second substrate. The passive component can be located between the first substrate and the second substrate. A height of the passive component can be is less than the distance between the first substrate and the second substrate. The second substrate can include a die interface configured for communication with a die. The die interface can be communicatively coupled to the passive component.

公开(公告)号：US20190050715A1

公开(公告)日：2019-02-14

申请号：US16147037

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Kooi Chi Ooi ,  Min Suet Lim ,  Denica Larsen ,  Lady Nataly Pinilla Pico ,  Divya Vijayaraghavan

IPC: G06N3/04 ,  G06K9/62 ,  G06N5/04 ,  G06N3/08 ,  G06F15/78 ,  G06F1/16 ,  G06F17/30 ,  G06N99/00

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve data training of a machine learning model using a field-programmable gate array (FPGA). An example system includes one or more computation modules, each of the one or more computation modules associated with a corresponding user, the one or more computation modules training first neural networks using data associated with the corresponding users, and FPGA to obtain a first set of parameters from each of the one or more computation modules, the first set of parameters associated with the first neural networks, configure a second neural network based on the first set of parameters, execute the second neural network to generate a second set of parameters, and transmit the second set of parameters to the first neural networks to update the first neural networks.