公开(公告)号：US20190103346A1

公开(公告)日：2019-04-04

申请号：US15845531

申请日：2017-12-18

申请人： Intel Corporation

发明人： Eng Huat Goh ,  Min Suet Lim ,  Jiun Hann Sir ,  Hoay Tien Teoh ,  Jimmy Huat Since Huang

IPC分类号： H01L23/498 ,  H05K1/18 ,  H01L21/56 ,  H01L23/538 ,  H01L23/522 ,  H01L23/00

摘要： An electronic package with passive components located between a first substrate and a second substrate. The electronic package can include a first substrate including a device interface for communication with an electronic device. An interposer can be electrically coupled to the first substrate. A second substrate can be offset from the first substrate at a distance. The second substrate can be electrically coupled to the first substrate through the interposer. A passive component can be attached to one of the first substrate or the second substrate. The passive component can be located between the first substrate and the second substrate. A height of the passive component can be is less than the distance between the first substrate and the second substrate. The second substrate can include a die interface configured for communication with a die. The die interface can be communicatively coupled to the passive component.

公开(公告)号：US20180366457A1

公开(公告)日：2018-12-20

申请号：US15781798

申请日：2015-12-16

申请人： Intel Corporation

发明人： Eng Huat Goh ,  Hoay Tien Teoh

IPC分类号： H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L23/367 ,  H01L23/538 ,  H01L21/48

CPC分类号： H01L25/18 ,  H01L21/4882 ,  H01L23/13 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/48 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/16251 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099

摘要： Donut-shaped Dynamic Random Access Memory (DRAM) includes a hole that fits around a processor, such that the DRAM and the processor are adjacent to one another on an Integrated Circuit (TC) package. In an embodiment, a heat spreader is mounted on top of the processor and covers a top of the DRAM without touching the DRAM.

公开(公告)号：US20220139814A1

公开(公告)日：2022-05-05

申请号：US17579186

申请日：2022-01-19

申请人： Intel Corporation

发明人： Eng Huat Goh ,  Min Suet Lim ,  Jiun Hann Sir ,  Hoay Tien Teoh ,  Jimmy Huat Since Huang

IPC分类号： H01L23/498 ,  H05K1/18 ,  H01L21/56 ,  H01L23/522 ,  H01L23/00 ,  H01L23/538

摘要： An electronic package with passive components located between a first substrate and a second substrate. The electronic package can include a first substrate including a device interface for communication with an electronic device. An interposer can be electrically coupled to the first substrate. A second substrate can be offset from the first substrate at a distance. The second substrate can be electrically coupled to the first substrate through the interposer. A passive component can be attached to one of the first substrate or the second substrate. The passive component can be located between the first substrate and the second substrate. A height of the passive component can be is less than the distance between the first substrate and the second substrate. The second substrate can include a die interface configured for communication with a die. The die interface can be communicatively coupled to the passive component.

公开(公告)号：US10861839B2

公开(公告)日：2020-12-08

申请号：US16531688

申请日：2019-08-05

申请人： Intel Corporation

发明人： Eng Huat Goh ,  Hoay Tien Teoh

IPC分类号： H01L25/18 ,  H01L23/48 ,  H01L25/065 ,  H01L25/10 ,  H01L23/13 ,  H01L23/538 ,  H01L23/36 ,  H01L23/00 ,  H01L21/48 ,  H01L23/367 ,  H01L25/00

摘要： Donut-shaped Dynamic Random Access Memory (DRAM) includes a hole that fits around a processor, such that the DRAM and the processor are adjacent to one another on an Integrated Circuit (IC) package. In an embodiment, a heat spreader is mounted on top of the processor and covers a top of the DRAM without touching the DRAM.

公开(公告)号：US09613920B2

公开(公告)日：2017-04-04

申请号：US14986542

申请日：2015-12-31

申请人： Intel Corporation

发明人： Eng Huat Goh ,  Hoay Tien Teoh

IPC分类号： H01L23/00 ,  H01L21/50 ,  H01L23/48 ,  H01L23/29 ,  H01L23/538 ,  H01L21/768 ,  H01L23/31

CPC分类号： H01L24/02 ,  H01L21/50 ,  H01L21/76898 ,  H01L23/295 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L2224/02311 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05024 ,  H01L2224/05567 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/2518 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/0105 ,  H01L2224/05552 ,  H01L2924/00

摘要： A microelectronic package having a first bumpless build-up layer structure adjacent an active surface and sides of a microelectronic device and a second bumpless build-up layer structure adjacent a back surface of the microelectronic device, wherein conductive routes are formed through the first bumpless build-up layer from the microelectronic device active surface to conductive routes in the second bumpless build-up layer structure and wherein through-silicon vias adjacent the microelectronic device back surface and extending into the microelectronic device are electrically connected to the second bumpless build-up layer structure conductive routes.

公开(公告)号：US11696409B2

公开(公告)日：2023-07-04

申请号：US16325659

申请日：2016-09-30

申请人： Intel Corporation

发明人： Tin Poay Chuah ,  Min Suet Lim ,  Hoay Tien Teoh ,  Mooi Ling Chang ,  Chin Lee Kuan

IPC分类号： H05K1/18 ,  H05K1/11 ,  H05K1/16

CPC分类号： H05K1/184 ,  H05K1/111 ,  H05K1/113 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K1/183 ,  H05K2201/0305 ,  H05K2201/09072 ,  H05K2201/10454

摘要： A printed circuit board (PCB) comprises a blind via and a discrete component vertically embedded within the blind via.

公开(公告)号：US11264315B2

公开(公告)日：2022-03-01

申请号：US15845531

申请日：2017-12-18

申请人： Intel Corporation

发明人： Eng Huat Goh ,  Min Suet Lim ,  Jiun Hann Sir ,  Hoay Tien Teoh ,  Jimmy Huat Since Huang

IPC分类号： H01L23/498 ,  H05K1/18 ,  H01L21/56 ,  H01L23/522 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H05K3/34

摘要： An electronic package with passive components located between a first substrate and a second substrate. The electronic package can include a first substrate including a device interface for communication with an electronic device. An interposer can be electrically coupled to the first substrate. A second substrate can be offset from the first substrate at a distance. The second substrate can be electrically coupled to the first substrate through the interposer. A passive component can be attached to one of the first substrate or the second substrate. The passive component can be located between the first substrate and the second substrate. A height of the passive component can be is less than the distance between the first substrate and the second substrate. The second substrate can include a die interface configured for communication with a die. The die interface can be communicatively coupled to the passive component.

公开(公告)号：US20190306978A1

公开(公告)日：2019-10-03

申请号：US16263370

申请日：2019-01-31

申请人： Intel Corporation

发明人： Eng Huat Goh ,  Hoay Tien Teoh

IPC分类号： H05K1/11 ,  H05K1/02 ,  H01L23/538 ,  H01L23/00 ,  H01L25/18

摘要： A jumper may be adapted to transmit an electrical signal. The jumper may be included in a system on a chip. The system on a chip may include a substrate, and the substrate may include one or more routing layers. The jumper may be included in the one or more routing layers of the substrate. A first interconnect may be positioned on a first side of the system on a chip, and a second interconnect may be positioned on a second side of the system on a chip. The jumper may be in electrical communication with the first interconnect, and may be in electrical communication with the second interconnect. The jumper may be electrically isolated from other components of the system on a chip, such as one or more die coupled to the substrate.

公开(公告)号：US09972589B1

公开(公告)日：2018-05-15

申请号：US15474293

申请日：2017-03-30

申请人： Intel Corporation

发明人： Eng Huat Goh ,  Min Suet Lim ,  Jiun Hann Sir ,  Seok Ling Lim ,  Hoay Tien Teoh

IPC分类号： H01L23/66 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01P3/08 ,  H01L23/528 ,  H01L23/522 ,  H01L25/065

CPC分类号： H01L23/66 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/17 ,  H01L2223/6627 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/19032 ,  H01P3/082 ,  H01L2224/81 ,  H01L2224/83

摘要： Described herein are integrated circuit structures having a package substrate with microstrip architecture as the uppermost layers and a surface conductive layer that is electrically connected to a ground plane internal to the package substrate, as well as related devices and methods. In one aspect of the present disclosure, an integrated circuit package substrate may have an internal ground plane, a dielectric layer, a microstrip signal layer as the top transmission line layer, a solder resist layer, and a surface conductive layer that is electrically connected to the internal ground plane in the package substrate. In another aspect of the present disclosure, an integrated circuit package substrate may include altering thicknesses of the dielectric and/or solder resist layers to optimize electrical performance by having the microstrip signal layer closer in proximity to the internal ground layer as compared to the surface conductive layer.

公开(公告)号：US20200027867A1

公开(公告)日：2020-01-23

申请号：US16531688

申请日：2019-08-05

申请人： Intel Corporation

发明人： Eng Huat Goh ,  Hoay Tien Teoh

IPC分类号： H01L25/18 ,  H01L23/48 ,  H01L25/065 ,  H01L25/10 ,  H01L23/13 ,  H01L23/538 ,  H01L23/36 ,  H01L23/00 ,  H01L21/48 ,  H01L23/367

摘要： Donut-shaped Dynamic Random Access Memory (DRAM) includes a hole that fits around a processor, such that the DRAM and the processor are adjacent to one another on an Integrated Circuit (IC) package. In an embodiment, a heat spreader is mounted on top of the processor and covers a top of the DRAM without touching the DRAM.