公开(公告)号：US20220075435A1

公开(公告)日：2022-03-10

申请号：US17359153

申请日：2021-06-25

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Pierce I-Jen Chuang ,  Phillip John Restle ,  Christos Vezyrtzis

IPC: G06F1/3206 ,  G06F1/28 ,  G06F1/30

Abstract: Techniques facilitating voltage management via on-chip sensors are provided. In one example, a computer-implemented method can comprise measuring, by a first processor core, power supply information. The computer-implemented method can also comprise measuring, by the first processor core, a value of an electrical current generated by the first processor core. Further, the computer-implemented method can comprise applying, by the first processor core, a mitigation technique at the first processor core in response to a determination that a combination of the power supply noise information and the value of the electrical current indicates a presence of a voltage noise at the first processor core.

公开(公告)号：US20220026972A1

公开(公告)日：2022-01-27

申请号：US16940171

申请日：2020-07-27

Applicant: International Business Machines Corporation

Inventor： Parth Sanjaybhai Shah ,  Ranjal Gautham Shenoy ,  Vaidyanathan Srinivasan ,  Alper Buyuktosunoglu ,  Augusto Vega ,  Pradip Bose

IPC: G06F1/324 ,  G06F1/3237 ,  G06F1/26

Abstract: A method, computer program product, and/or system associates a number of tokens with a plurality of frequency domains (for example, cores) of a central processing unit (CPU) computer chip. The number of tokens allotted to the CPU is based on the CPU power budget. Cores are organized as a ring topology. A token pool traverses the ring, picks up excess tokens from cores having excess tokens, and gives the tokens to cores that need additional tokens. Tokens acquired by a core allows the core to increase operating frequency by an increment represented by the tokens. Consequently, power usage is weighted toward heavily loaded cores and away from lightly loaded cores. Overall power usage of the CPU remains within a power budget. The method budgets power optimally to sustain turbo frequencies for longer durations by not allowing control units to increase frequency in absence of any useful high frequency benefiting workload.

公开(公告)号：US11073884B2

公开(公告)日：2021-07-27

申请号：US15814069

申请日：2017-11-15

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Pierce I-Jen Chuang ,  Phillip John Restle ,  Christos Vezyrtzis

IPC: G06F1/28 ,  G06F1/32 ,  G06F1/3206 ,  G06F1/30

Abstract: Techniques facilitating voltage management via on-chip sensors are provided. In one example, a computer-implemented method can comprise measuring, by a first processor core, power supply information. The computer-implemented method can also comprise measuring, by the first processor core, a value of an electrical current generated by the first processor core. Further, the computer-implemented method can comprise applying, by the first processor core, a mitigation technique at the first processor core in response to a determination that a combination of the power supply noise information and the value of the electrical current indicates a presence of a voltage noise at the first processor core.

公开(公告)号：US10690723B2

公开(公告)日：2020-06-23

申请号：US16398972

申请日：2019-04-30

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Schuyler Eldridge ,  Karthik V. Swaminathan ,  Yazhou Zu

IPC: G01R31/3183 ,  G06F30/00 ,  G01R31/317

Abstract: Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.

公开(公告)号：US10558518B2

公开(公告)日：2020-02-11

申请号：US15810336

申请日：2017-11-13

Applicant: International Business Machines Corporation

Inventor： Prashant Jayaprakash Nair ,  Alper Buyuktosunoglu ,  Pradip Bose

IPC: G06F11/10 ,  G06F11/07 ,  G06F3/06 ,  G11C16/34 ,  G06F1/324 ,  G06F1/3296

Abstract: A computer monitors a memory system during operation. The computer detects a first number of errors in the memory system. The computer determines that the first number of errors is below an error level threshold. The computer lowers a first group of one or more memory parameters of the memory system by a first amount. After the lowering of one or more memory parameters by the first amount, the computer detects a second number of errors in the memory system. The computer determines that the second number of errors is above the error level threshold. The computer raises a second group of one or more memory parameters of the memory system by a second amount.

公开(公告)号：US10444812B2

公开(公告)日：2019-10-15

申请号：US15605154

申请日：2017-05-25

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Hubertus Franke ,  Priyanka Tembey ,  Dilma M. Da Silva

IPC: G06F1/32 ,  G06F1/3206 ,  G06F9/50 ,  G06F9/48 ,  G06F1/26 ,  G06F1/329 ,  G06F1/3203

Abstract: Power consumption in a microprocessor platform is managed by setting a peak power level for power consumed by a multi-core microprocessor platform executing multi-threaded applications. The multi-core microprocessor platform contains a plurality of physical cores, and each physical core is configurable into a plurality of logical cores. A simultaneous multithreading level in at least one physical core is adjusted by changing the number of logical cores on that physical core in response to a power consumption level of the multi-core microprocessor platform exceeding the peak power level. Performance and power data based on simultaneous multi-threading levels are used in selecting the physical core to be adjusted.

公开(公告)号：US20190113572A1

公开(公告)日：2019-04-18

申请号：US15787473

申请日：2017-10-18

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Schuyler Eldridge ,  Karthik V. Swaminathan ,  Yazhou Zu

IPC: G01R31/3183 ,  G01R31/317

CPC classification number: G01R31/318357 ,  G01R31/31704

Abstract: Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.

公开(公告)号：US10075875B2

公开(公告)日：2018-09-11

申请号：US14868717

申请日：2015-09-29

Applicant: International Business Machines Corporation

Inventor： Alper Buyuktosunoglu ,  Pradip Bose ,  Augusto J. Vega

IPC: H04W28/08 ,  H04W28/02 ,  H04L12/26

CPC classification number: H04W28/08 ,  H04L43/16 ,  H04W28/0226

Abstract: A computer-implemented method includes determining, by a first base station, that the first base station is overloaded with connections from mobile devices. Responsive to the first base station being overloaded, a status update may be received, by the first base station, from each of a plurality of base stations, where each base station is configured to provide connections to a plurality of mobile devices. Responsive to the first base station being overloaded, a second base station may be selected, by a computer processor of the first base station, from among the plurality of base stations. Responsive to the first base station being overloaded, the second base station may be instructed, by the first base station, to relocate from a first position to a new position closer to the first base station. The plurality of base stations automatically relocate to load-balance connections from the plurality of mobile devices.

公开(公告)号：US10042642B2

公开(公告)日：2018-08-07

申请号：US15412361

申请日：2017-01-23

Applicant: International Business Machines Corporation

Inventor： Ramon Bertran ,  Pradip Bose ,  Alper Buyuktosunoglu ,  Timothy J. Slegel

IPC: G06F17/50 ,  G06F9/30 ,  G06F11/34 ,  G06F11/30 ,  G06F15/78 ,  G06F11/00 ,  G06F9/455 ,  G06F13/10 ,  G06F13/12 ,  G01R31/28 ,  G06F9/44

Abstract: One aspect is a method that includes analyzing, by a processor of an analysis system, an instruction set architecture of a targeted complex-instruction set computer (CISC) processor to generate an instruction set profile for each CISC architectural instruction variant of the instruction set architecture. A combination of instruction sequences for the targeted CISC processor is determined from the instruction set profile that corresponds to a desired stressmark type. The desired stressmark type defines a metric representative of functionality of interest of the targeted CISC processor. Performance of the targeted CISC processor is monitored with respect to the desired stressmark type while executing each of the instruction sequences. The targeted CISC processor is stress tested based on executing at least one of the instruction sequences identified as most closely aligning with the desired stressmark type.

公开(公告)号：US09933844B2

公开(公告)日：2018-04-03

申请号：US14953705

申请日：2015-11-30

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Hans M. Jacobson ,  Augusto J. Vega

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/329 ,  Y02D10/24 ,  Y02D50/20

Abstract: Embodiments relate to clustering execution in a processing system. An aspect includes accessing a control flow graph that defines a data dependency and an execution sequence of a plurality of tasks of an application that executes on a plurality of system components. The execution sequence of the tasks in the control flow graph is modified as a clustered control flow graph that clusters active and idle phases of a system component while maintaining the data dependency. The clustered control flow graph is sent to an operating system, where the operating system utilizes the clustered control flow graph for scheduling the tasks.