公开(公告)号：US20180089074A1

公开(公告)日：2018-03-29

申请号：US15279279

申请日：2016-09-28

Applicant: Intel Corporation

Inventor： Peng Li ,  Sanjeev N. Trika

IPC: G06F12/02

CPC classification number: G06F12/0238 ,  G06F2212/1008 ,  G06F2212/1044 ,  G06F2212/202 ,  G06F2212/7201 ,  G06F2212/7207 ,  G06F2212/7208

Abstract: Examples may include techniques to manage key-value storage at a memory or storage device. A key-value command such as a put key-value command is received and data for a key and data for a value included in the put key-value command may be stored in one or more first non-volatile memory (NVM) devices maintained at a memory or storage device. A hash-to-physical (H2P) table or index is stored in one or more second NVM devices maintained at the memory or storage device. The H2P table or index is utilized to locate and read the data for the key and the data for the value responsive to other key-value commands.

公开(公告)号：US11854931B2

公开(公告)日：2023-12-26

申请号：US16721807

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Chia-Pin Chiu ,  Peng Li ,  Shankar Devasenathipathy

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/42 ,  H01L23/373 ,  H01L23/538 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/367 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/3736 ,  H01L23/42 ,  H01L23/5386 ,  H01L24/32 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2225/06589

Abstract: Embodiments include semiconductor packages and a method to form such packages. A semiconductor package includes first and second bottom dies on a package substrate. The semiconductor package includes first top dies on the first bottom die, second top dies on the second bottom die, and a pedestal on the first and second bottom dies. The pedestal comprises a high thermal conductive material and is positioned on a region of top surfaces of the first and second bottom dies. The semiconductor package includes an encapsulation layer over the first and second bottom dies, and surrounds the first and second top dies and the pedestal. The semiconductor package includes a TIM over the first and second top dies, pedestal, and encapsulation layer, and an integrated heat spreader (IHS) over the TIM. The pedestal is on a periphery region of the top surfaces of the first and second bottom dies.

公开(公告)号：US20220244477A1

公开(公告)日：2022-08-04

申请号：US17723174

申请日：2022-04-18

Applicant: Intel Corporation

Inventor： Peng Li ,  Joel Martinez ,  Jon Long

IPC: G02B6/43 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H04B10/40

Abstract: A multichip package may include at least a package substrate, a main die mounted on the package substrate, a transceiver die mounted on the package substrate, and an optical engine die mounted on the package substrate. The main die may communicate with the transceiver die via a first high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die may communicate with the optical engine die via a second high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die has physical-layer circuits that directly drive the optical engine. An optical cable can be connected directly to the optical engine of the multichip package.

公开(公告)号：US11327259B2

公开(公告)日：2022-05-10

申请号：US15835177

申请日：2017-12-07

Applicant: Intel Corporation

Inventor： Peng Li ,  Joel Martinez ,  Jon Long

IPC: G02B6/43 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H04B10/40

Abstract: A multichip package may include at least a package substrate, a main die mounted on the package substrate, a transceiver die mounted on the package substrate, and an optical engine die mounted on the package substrate. The main die may communicate with the transceiver die via a first high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die may communicate with the optical engine die via a second high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die has physical-layer circuits that directly drive the optical engine. An optical cable can be connected directly to the optical engine of the multichip package.

公开(公告)号：US11101925B2

公开(公告)日：2021-08-24

申请号：US15842331

申请日：2017-12-14

Applicant: Intel Corporation

Inventor： Martin Langhammer ,  Peng Li ,  Masashi Shimanouchi

IPC: H04L1/00 ,  H03M13/15 ,  H03M13/00

Abstract: Network communication systems may employ coding schemes to provide error checking and/or error correction. Such schemes may include parity or check symbols in a message that may add redundancy, which may be used to check for errors. For example, Ethernet may employ forward error correction (FEC) schemes using Reed-Solomon codes. An increase in the number of parity symbols may increase the power of the error-correcting scheme, but may lead to an increased in latencies. Encoders and decoders that may be configured in a manner to produce variable-length messages while preserving compatibility with network standards are described. Decoders described herein may be able to verify long codewords by checking short codes and integrating the results. Encoders described herein may be able to generate codewords in multiple formats without replicating large segments of the circuitry.

公开(公告)号：US11042323B2

公开(公告)日：2021-06-22

申请号：US16457982

申请日：2019-06-29

Applicant: Intel Corporation

Inventor： Peng Li ,  Jawad B. Khan ,  Sanjeev N. Trika

IPC: G06F3/06 ,  G06F12/1081 ,  G06F12/1009

Abstract: A host-managed storage device includes an offload capability that enables the host to offload all or a portion of a defrag operation to the storage device. Rather than issuing read, write or copy operations and commands to relocate data to the host's DRAM, the host assembles a defrag operation command descriptor for the storage device controller. The command descriptor includes a defrag bitmap that can be directly accessed by the storage device controller to conduct the defrag operation entirely on the storage device at band granularity, without consuming host CPU cycles or host memory. The reduction in host operations/commands achieved by offloading defragmentation to the storage device is on the order of at least a thousand-fold reduction.

公开(公告)号：US20210020537A1

公开(公告)日：2021-01-21

申请号：US16516692

申请日：2019-07-19

Applicant: Intel Corporation

Inventor： Sergio Antonio Chan Arguedas ,  Manish Dubey ,  Peng Li ,  Aravindha R. Antoniswamy ,  Anup Pancholi

IPC: H01L23/367 ,  H01L23/00

Abstract: Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A solder thermal interface material (STIM) may be coupled with the die such that the die is between the STIM and the package substrate. An integrated heat spreader (IHS) may be coupled with the STIM such that the STIM is between the IHS and the die, and the IHS may include a feature that is to control bleed-out of the STIM during STIM reflow based on surface tension of the STIM. Other embodiments may be described or claimed.

公开(公告)号：US10884916B2

公开(公告)日：2021-01-05

申请号：US15939398

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Sanjeev Trika ,  Jawad Khan ,  Peng Li ,  Myron Loewen

IPC: G06F12/02 ,  G06F3/06 ,  G06F21/62 ,  G06F16/16 ,  G06F16/18 ,  G11C13/00

Abstract: An embodiment of a mass storage apparatus may include first non-volatile media, second non-volatile media which provides a relatively larger write granularity as compared to the first non-volatile media, and logic communicatively coupled to the first and second non-volatile media to direct an access request to one of the first non-volatile media and the second non-volatile media based on an indication from an operating system. An embodiment of a host computing apparatus may include a processor, memory communicatively coupled to the processor, and logic communicatively coupled to the processor to provide an indication for a file system-related access request to a mass storage device based on a granularity size for the file system-related access request. Other embodiments are disclosed and claimed.

公开(公告)号：US10761819B2

公开(公告)日：2020-09-01

申请号：US16070890

申请日：2016-02-23

Applicant: Intel Corporation

Inventor： Zhigang Gong ,  Wenqing Fu ,  Peng Li ,  Can Que ,  Zhiwen Wu

IPC: G06F8/41

Abstract: An input data structure of a first size may be converted to a plurality of data structures of a second size smaller than the first size. The data structures of the second size are realigned such that each of the plurality of data structures fits in one cache line. The realigned data structures are compiled for use in a vector machine.

公开(公告)号：US20200097405A1

公开(公告)日：2020-03-26

申请号：US16585892

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Peng Li ,  Jawad B. Khan ,  Sanjeev N. Trika

IPC: G06F12/06 ,  G11C7/10 ,  G05B19/045

Abstract: An embodiment of a semiconductor package apparatus may include technology to provide a first interface between a first storage device and a host device, and provide a second interface directly between the first storage device and a second storage device. Other embodiments are disclosed and claimed.