公开(公告)号：US20230418604A1

公开(公告)日：2023-12-28

申请号：US17850044

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Pushkar Ranade ,  Wilfred Gomes ,  Sagar Suthram

IPC: G06F9/30 ,  G06F9/445 ,  G06F9/50

CPC classification number: G06F9/30036 ,  G06F9/5016 ,  G06F9/44505

Abstract: In one embodiment, a memory includes a die having: one or more memory layers having a plurality of banks to store data; and at least one other layer comprising at least one reconfigurable vector processor, the at least one reconfigurable vector processor to perform a vector computation on input vector data obtained from at least one bank of the plurality of banks and provide processed vector data to the at least one bank. Other embodiments are described and claimed.

公开(公告)号：US20230413547A1

公开(公告)日：2023-12-21

申请号：US17843867

申请日：2022-06-17

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Abhishek A. Sharma ,  Wilfred Gomes ,  Anand S. Murthy ,  Tahir Ghani ,  Pushkar Sharad Ranade

IPC: H01L27/1156 ,  H01L27/11524

CPC classification number: H01L27/1156 ,  H01L27/11524

Abstract: IC devices implementing 2T memory cells with source-drain coupling in one transistor, and related assemblies and methods, are disclosed herein. In particular, 2T memory cells presented herein use first and second transistors arranged so that source and drain terminals of the second transistor are coupled to one another. A memory state may be represented by charge indicative of the bit value stored in the second transistor, while the first transistor may serve as a switch to control access to the second transistor. 2T memory cells with source-drain coupling in one transistor provide a promising way to increasing memory cell densities, drive current, and design flexibility in making electrical connections to, or between, various transistor terminals and control lines of memory arrays, thus providing good scalability in the number of 2T memory cells included in memory arrays.

公开(公告)号：US20230318825A1

公开(公告)日：2023-10-05

申请号：US17708431

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Sagar Suthram ,  Pushkar Ranade ,  Wilfred Gomes

IPC: H04L9/08 ,  G06F21/72

CPC classification number: H04L9/0894 ,  G06F21/72 ,  H04L9/0819

Abstract: In one embodiment, an apparatus includes: at least one core to execute operations on data; a cryptographic circuit to perform cryptographic operations; a static random access memory (SRAM) coupled to the at least one core; and a ferroelectric memory coupled to the at least one core. In response to a read request, the SRAM is to provide an encryption key to the cryptographic circuit and the ferroelectric memory is to provide encrypted data to the cryptographic circuit, the encryption key associated with the encrypted data. Other embodiments are described and claimed.

公开(公告)号：US20230317794A1

公开(公告)日：2023-10-05

申请号：US17712057

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Wilfred Gomes ,  Sagar Suthram ,  Pushkar Ranade ,  Rajabali Koduri

IPC: H01L29/10 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L23/427

CPC classification number: H01L29/1037 ,  H01L27/0886 ,  H01L21/823412 ,  H01L21/823431 ,  H01L29/7851 ,  H01L29/66795 ,  H01L23/427 ,  H01L29/247

Abstract: Narrow-channel, non-planar transistors and their manufacture on integrated circuit dies. A method includes forming channel portions of transistors from sidewall spacers by removing backbone features and coupling a gate structure, a source, and a drain to the channel portions. An integrated circuit die includes a gate structure, a source, and a drain coupled to pair-symmetric channel portions with sidewalls of differing heights. A method includes iteratively etching away portions of semiconductor material not covered by a mask or a passivation layer, revealing a channel portion by removing the mask and passivation layer, and coupling a gate structure, a source, and a drain to the channel portion. An integrated circuit die includes a gate structure, a source, and a drain coupled to a channel portion with vertically alternating, greater and lesser widths.

公开(公告)号：US20230290831A1

公开(公告)日：2023-09-14

申请号：US17690358

申请日：2022-03-09

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Wilfred Gomes ,  Ravi Pillarisetty ,  Willy Rachmady ,  Sagar Suthram ,  Pushkar Sharad Ranade ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/10 ,  H01L29/45 ,  H01L29/06 ,  H01L29/423 ,  H01L29/40

CPC classification number: H01L29/1033 ,  H01L29/45 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/401 ,  H01L27/10826

Abstract: The scaling of features in ICs has been a driving force behind an ever-growing semiconductor industry. As transistors of the ICs become smaller, their gate lengths become smaller, leading to undesirable short-channel effects such as poor leakage, poor subthreshold swing, drain-induced barrier lowering, etc. Reducing transistor dimensions at the gate allows keeping the footprint of the transistor relatively small and comparable to what could be achieved implementing a transistor with a shorter gate length while effectively increasing transistor's effective gate length and thus reducing the negative impacts of short-channel effects. This architecture may be optimized even further if transistors are to be operated at relatively low temperatures, e.g., below 200 Kelvin degrees or lower.

公开(公告)号：US20230261107A1

公开(公告)日：2023-08-17

申请号：US17672332

申请日：2022-02-15

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Tahir Ghani ,  Wilfred Gomes ,  Sagar Suthram ,  Pushkar Sharad Ranade ,  Willy Rachmady ,  Ravi Pillarisetty ,  Anand S. Murthy

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/40 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/78391 ,  H01L29/516 ,  H01L29/401 ,  H01L29/7851 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

Abstract: Disclosed herein are transistor gate-channel arrangements with transistor gate stacks that include dipole layers, and related methods and devices. Transistor gate stacks disclosed herein include a multilayer gate oxide having both a high-k dielectric and a dipole layer. In some embodiments, a thin dipole layer may directly border a channel material of choice and may be between the channel material and the high-k dielectric. In other embodiments, a passivation layer may spontaneously form between the dipole layer and the channel material. In still other embodiments, the high-k dielectric may be between the dipole layer and the channel material. Temporary polarization provided by the dipole layer may increase the effective dielectric constant of the high-k dielectric and may allow to use thinner high-k dielectrics and/or high-k dielectrics of suboptimal quality while maintaining transistor performance in terms of, e.g., gate leakage, carrier mobility, and subthreshold swing.

公开(公告)号：US20250107108A1

公开(公告)日：2025-03-27

申请号：US18473421

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Sagar Suthram ,  Wilfred Gomes ,  Tahir Ghani ,  Anand S. Murthy ,  Pushkar Sharad Ranade

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: An IC device may include memory layers bonded to a logic layer with inclination. An angle between a memory layer and the logic layer may be in a range from approximately 0 to approximately 90 degrees. The memory layers may be over the logic layer. The IC device may include one or more additional logic layers that are parallel to a memory layer or perpendicular to a memory layer. The one or more additional logic layers may be over the logic layer. A memory layer may include memory cells. The logic layer may include logic circuits (e.g., sense amplifier, word line driver, etc.) that control the memory cells. Bit lines (or word lines) in different memory layers may be coupled to each other. A bit line and a word line in a memory layer may be controlled by logic circuits in different logic layers.

公开(公告)号：US20250107107A1

公开(公告)日：2025-03-27

申请号：US18471402

申请日：2023-09-21

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Sagar Suthram ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Anand S. Murthy ,  Tahir Ghani

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: An IC device may include memory layers over a logic layer. A memory layer may include memory arrays and one or more peripheral circuits coupled to the memory arrays. A memory array may include memory cells arranged in rows and columns. A row of memory cells may be associated with a word line. A column of memory cells may be associated with a bit line. The logic layer includes one or more logic circuits that can control data read operations and data write operations of the memory layers. The logic layer may also include a power interconnect, which facilitates power delivery to the memory layers, and a signal interconnect, which facilitates signal transmission within the IC device. The IC device may further include vias that couple the memory layers to the logic layer. Each via may be connected to one or more memory layers and the logic layer.

公开(公告)号：US20250079398A1

公开(公告)日：2025-03-06

申请号：US18460817

申请日：2023-09-05

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Wilfred Gomes ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Pushkar Sharad Ranade ,  Nitin A. Deshpande ,  Abhishek A. Sharma

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H10B80/00

Abstract: Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including conductive traces that are parallel to the first and second surfaces and exposed at the third surface; a second IC die having a fourth surface and including voltage regulator circuitry; and a third IC die having a fifth surface, wherein the third surface of the first IC die is electrically coupled to the fifth surface of the third IC die by first interconnects, the fourth surface of the second IC die is electrically coupled to the fifth surface of the third IC die by second interconnects, and the first IC die is electrically coupled to the second IC die by conductive pathways in the third IC die.

公开(公告)号：US20240222328A1

公开(公告)日：2024-07-04

申请号：US18148543

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Wilfred Gomes ,  Nisha Ananthakrishnan ,  Kemal Aygun ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10B12/00

CPC classification number: H01L25/0657 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295 ,  H10B12/39

Abstract: Embodiments of a microelectronic assembly include: a first integrated circuit (IC) die having a first memory circuit and a second memory circuit, a second IC die; a third IC die; and a package substrate. The first IC die comprises: a first portion comprising a first active region and a first backend region in contact with the first active region; and a second portion comprising a second active region and a second backend region in contact with the second active region. The second portion is surrounded by the first portion in plan view, the first memory circuit is in the first portion, the second memory circuit is in the second portion, the first active region comprises transistors that are larger than transistors in the second active region, and the first backend region comprises conductive traces that have a larger pitch than conductive traces in the second backend region.