公开(公告)号：US12067898B2

公开(公告)日：2024-08-20

申请号：US17256105

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Shao-Wen Yang ,  Addicam V. Sanjay ,  Karthik Veeramani ,  Gabriel L Silva ,  Marcos P. Da Silva ,  Jose A. Avalos ,  Stephen T. Palermo ,  Glen J. Anderson ,  Meng Shi ,  Benjamin W. Bair ,  Pete A. Denman ,  Reese L. Bowes ,  Rebecca A. Chierichetti ,  Ankur Agrawal ,  Mrutunjayya Mrutunjayya ,  Gerald A. Rogers ,  Shih-Wei Roger Chien ,  Lenitra M. Durham ,  Giuseppe Raffa ,  Irene Liew ,  Edwin Verplanke

IPC: G06F9/38 ,  G06F9/455 ,  G06T19/00 ,  G09B5/06

CPC classification number: G09B5/067 ,  G06F9/3877 ,  G06F9/45558 ,  G06T19/006 ,  G06F2009/45562 ,  G06F2009/4557 ,  G06F2009/45595

Abstract: In one embodiment, an apparatus comprises a memory and a processor. The memory is to store sensor data, wherein the sensor data is captured by a plurality of sensors within an educational environment. The processor is to: access the sensor data captured by the plurality of sensors: identify a student within the educational environment based on the sensor data: detect a plurality of events associated with the student based on the sensor data, wherein each event is indicative of an attention level of the student within the educational environment: generate a report based on the plurality of events associated with the student; and send the report to a third party associated with the student.

公开(公告)号：US11711267B2

公开(公告)日：2023-07-25

申请号：US16798946

申请日：2020-02-24

Applicant: Intel Corporation

Inventor： Valerie J. Parker ,  Neal Conrad Oliver ,  Stephen T. Palermo ,  Hari K. Tadepalli

IPC: H04L41/082 ,  H04L41/5006 ,  H04L41/16 ,  G06F16/18 ,  H04W48/18 ,  G06F9/455 ,  H04L9/06 ,  G06F16/182 ,  H04L9/00

CPC classification number: H04L41/082 ,  G06F9/45558 ,  G06F16/1805 ,  G06F16/1824 ,  H04L9/0637 ,  H04L41/16 ,  H04L41/5006 ,  H04W48/18 ,  G06F2009/45595 ,  H04L9/50

Abstract: Various systems and methods for implementing an edge computing system to realize 5G network slices with blockchain traceability for informed 5G service supply chain are disclosed. A system configured to track network slicing operations includes memory and processing circuitry configured to select a network slice instance (NSI) from a plurality of available NSIs based on an NSI type specified by a client node. The available NSIs uses virtualized network resources of a first network resource provider. The client node is associated with the selected NSI. The utilization of the network resources by the plurality of available NSIs is determined using an artificial intelligence (AI)-based network inferencing function. A ledger entry of associating the selected NSI with the client node is recorded in a distributed ledger, which further includes a second ledger entry indicating allocations of resource subsets to each of the NSIs based on the utilization.

公开(公告)号：US20230062253A1

公开(公告)日：2023-03-02

申请号：US17883011

申请日：2022-08-08

Applicant: Intel Corporation

Inventor： Mrittika Ganguli ,  Stephen T. Palermo ,  Valerie J. Parker

IPC: H04L67/10 ,  H04L67/12

Abstract: Various systems and methods for implementing a multi-access edge computing (MEC) based system to realize 5G Network Edge and Core Service Dimensioning using Machine Learning and other Artificial Intelligence Techniques, for improved operations and usage of computing and networking resources, and are disclosed herein. In an example, processing circuitry of a compute node on a network is used to analyze execution of an application to obtain operational data. The compute node then may modularize functions of the application based on the operational data to construct modularized functions. A phase transition graph is constructed using a machine-learning based analysis, the phase transition graph representing state transitions from one modularized function to another modularized function, where the phase transition graph is used to dimension the application by distributing the modularized functions across the network.

公开(公告)号：US20220197685A1

公开(公告)日：2022-06-23

申请号：US17392861

申请日：2021-08-03

Applicant: Intel Corporation

Inventor： Stephen T. Palermo ,  Gerald Rogers ,  Shih-Wei Roger Chien ,  Namakkal Venkatesan ,  Rajesh Gadiyar

IPC: G06F9/455 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/0811 ,  G06F9/50 ,  G06F9/38

Abstract: Technologies for application-specific network acceleration include a computing device including a processor and an accelerator device such as a field-programmable gate array (FPGA). The processor and the accelerator device are coupled via a coherent interconnect and may be included in a multi-chip package. The computing device binds a virtual machine executed by the processor with an application function unit of the accelerator device via the coherent interconnect. The computing device processes network application data with the virtual machine and the application function unit within a coherency domain maintained with the coherent interconnect. Processing the network data may include processing a packet of a network flow by the virtual machine and processing subsequent packets of the network flow by the application function unit. Other embodiments are described and claimed.

公开(公告)号：US11086650B2

公开(公告)日：2021-08-10

申请号：US15904371

申请日：2018-02-25

Applicant: Intel Corporation

Inventor： Stephen T. Palermo ,  Gerald Rogers ,  Shih-Wei Roger Chien ,  Namakkal Venkatesan ,  Rajesh Gadiyar

IPC: G06F9/455 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/0811 ,  G06F9/50 ,  G06F9/38

Abstract: Technologies for application-specific network acceleration include a computing device including a processor and an accelerator device such as a field-programmable gate array (FPGA). The processor and the accelerator device are coupled via a coherent interconnect and may be included in a multi-chip package. The computing device binds a virtual machine executed by the processor with an application function unit of the accelerator device via the coherent interconnect. The computing device processes network application data with the virtual machine and the application function unit within a coherency domain maintained with the coherent interconnect. Processing the network data may include processing a packet of a network flow by the virtual machine and processing subsequent packets of the network flow by the application function unit. Other embodiments are described and claimed.

公开(公告)号：US20210117224A1

公开(公告)日：2021-04-22

申请号：US17134305

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Stephen T. Palermo ,  Krishnamurthy Jambur Sathyanarayana ,  Sean Harte ,  Thomas Long ,  Eliezer Tamir ,  Hari K. Tadepalli

IPC: G06F9/455 ,  H04L29/08

Abstract: Disclosed is a source host including a processor. The processor operates a virtual machine (VM) to communicate network traffic over a communication link. The processor also initiates migration of the VM to a destination host. The processor also suspends the VM during migration of the VM to the destination host. The source host also includes a live migration circuit coupled to the processor. The live migration circuit manages a session associated with the communication link while the VM is suspended during migration. The live migration circuit buffers changes to a session state and transfers the buffered session state changes to the destination host for replay after the VM is reactivated on the destination host. The live migration circuit keeps the sessions alive during migration to alleviate connection losses.

公开(公告)号：US10127072B2

公开(公告)日：2018-11-13

申请号：US15874266

申请日：2018-01-18

Applicant: Intel Corporation

Inventor： Stephen T. Palermo ,  Scott P. Dubal ,  Trevor Cooper ,  Anjali S. Jain ,  Iosif Gasparakis ,  Jr-Shian Tsai ,  Mike Bursell ,  Pradeepsunder Ganesh ,  Parthasarathy Sarangam ,  Jesse C. Brandeburg

IPC: G06F9/455 ,  G06F9/50

Abstract: The present disclosure is directed to enhanced virtual function capabilities in a virtualized network environment. In general, devices may comprise physical and virtualized resources. The physical resources may comprise at least a network adaptor that may handle incoming data from a network and outgoing data to the network. The virtualized resources may comprise at least one virtual machine (VM) and a corresponding interface. The corresponding interface may be one of a physical interface, a virtual interface or a “super” virtual interface. The physical interface may provide a first set of capabilities allowing the VM to access (e.g., control) at least the network adaptor. The virtual interface may provide a second set of capabilities that is a subset of the first set. The super virtual interface may provide a third set of capabilities including the second set of capabilities and at least one additional capability from the first set of capabilities.

公开(公告)号：US20180246768A1

公开(公告)日：2018-08-30

申请号：US15754517

申请日：2015-10-21

Applicant: Intel Corporation

Inventor： Stephen T. Palermo ,  Soo Jin Tan ,  Valerie Young ,  Hassnaa Moustafa

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/455

CPC classification number: G06F9/5044 ,  G06F9/45558 ,  G06F9/4881 ,  G06F2009/45595 ,  H04L12/66 ,  H04L43/0817 ,  H04L67/12 ,  H04L67/16

Abstract: Embodiments of a system and method for dynamic hardware acceleration are generally described herein. A method may include identifying a candidate task from a plurality of tasks executing in an operating environment, the operating environment within a hardware enclosure, the candidate task amenable to hardware optimization, instantiating, in response to identifying the candidate task, a hardware component in the operating environment to perform hardware optimization for the task, the hardware component being previously inaccessible to the operating environment, and executing, by the operating environment, a class of tasks amenable to the hardware optimization on the hardware component.

公开(公告)号：US10048977B2

公开(公告)日：2018-08-14

申请号：US14978569

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Stephen T. Palermo ,  Thomas E. Willis ,  Kapil Sood ,  Ilango S. Ganga ,  Scott P. Dubal ,  Pradeepsunder Ganesh ,  Jesse C. Brandeburg

IPC: G06F9/455 ,  H04L12/931

Abstract: Methods and Apparatus for Multi-Stage VM Virtual Network Function and Virtual Service Function Chain Acceleration for NFV and needs-based hardware acceleration. Compute platform hosting virtualized environments including virtual machines (VMs) running service applications performing network function virtualization (NFV) employ Field Programmable Gate Array (FPGA) to provide a hardware-based fast path for performing VM-to-VM and NFV-to-NFV transfers. The FPGAs, along with associated configuration data are also configured to support dynamic assignment and performance of hardware-acceleration to offload processing tasks from processors in virtualized environments, such as cloud data centers and the like.