公开(公告)号：US06389526B1

公开(公告)日：2002-05-14

申请号：US09382360

申请日：1999-08-24

申请人： James B. Keller ,  Dale Gulick ,  Larry Hewitt ,  Geoffrey Strongin

发明人： James B. Keller ,  Dale Gulick ,  Larry Hewitt ,  Geoffrey Strongin

IPC分类号： G06F1316

CPC分类号： G06F15/167 ,  G06F13/24

摘要： A circuit and method is provided for selectively stalling interrupt requests originating devices coupled to a multiprocessor system. The multiprocessor system includes a plurality of circuit nodes each one of which is coupled to an individual memory. An I/O bridge coupled to a first circuit node is configured to generate non-coherent memory access command packets and non-coherent interrupt command packets. The first circuit node also generates a coherent interrupt command packet in response to receiving the non-coherent interrupt command packet. The first circuit node transmits the coherent interrupt command packet to another circuit node, possibly the second circuit node. However, the transmission of the coherent interrupt command packet may be delayed. Any delay in transmission is based on a comparison of the pipe identifications of the non-coherent command packets.

摘要翻译： 提供了一种电路和方法，用于选择性地停止与多处理器系统耦合的发起设备的中断请求。 多处理器系统包括多个电路节点，每个电路节点都耦合到单独的存储器。 耦合到第一电路节点的I / O桥被配置为生成非相干存储器访问命令分组和非相干中断命令分组。 第一电路节点还响应于接收到非相干中断命令分组而产生相干中断命令分组。 第一电路节点将相干中断命令分组发送到另一个电路节点，可能是第二电路节点。 然而，相干中断命令分组的传输可能被延迟。 传输的任何延迟都是基于非相干命令包的管道标识的比较。

公开(公告)号：US06360314B1

公开(公告)日：2002-03-19

申请号：US09115186

申请日：1998-07-14

申请人： David Arthur James Webb, Jr. ,  James B. Keller ,  Derrick R. Meyer

发明人： David Arthur James Webb, Jr. ,  James B. Keller ,  Derrick R. Meyer

IPC分类号： G06F938

CPC分类号： G06F9/3834 ,  G06F9/3826

摘要： A bypass mechanism is disclosed for a computer system that executes load and store instructions out of order. The bypass mechanism compares the address of each issuing load instruction with a set of recent store instructions that have not yet updated memory. A match of the recent stores provides the load data instead of having to retrieve the data from memory. A store queue holds the recently issued stores. Each store queue entry and the issuing load includes a data size indicator. Subsequent to a data bypass, the data size indicator of the issuing load is compared against the data size indicator of the matching store queue entry. A trap is signaled when the data size indicator of the issuing load differs from the data size indicator of the matching store queue entry. The trap signal indicates that the data provided by the bypass mechanism was insufficient to satisfy the requirements of the load instruction. The bypass mechanism also operates in cases in which multiple prior stores to the same address are pending when a load that needs to read that address issues.

摘要翻译： 公开了一种用于执行装载和存储指令的计算机系统的旁路机构。 旁路机制将每个发布加载指令的地址与尚未更新内存的一组最近的存储指令进行比较。 最近的商店的匹配提供了加载数据，而不是从内存中检索数据。 商店队列持有最近发布的商店。 每个存储队列条目和发布加载包括数据大小指示符。 在数据旁路之后，将发布负载的数据大小指示符与匹配存储队列条目的数据大小指示符进行比较。 当发布负载的数据大小指示符与匹配的存储队列条目的数据大小指示符不同时，用信号通知陷阱。 陷阱信号表示旁路机构提供的数据不足以满足加载指令的要求。 在需要读取该地址的负载发生问题的情况下，旁路机制还可以在多个先前存储到同一地址的情况下进行操作。

公开(公告)号：US06253285B1

公开(公告)日：2001-06-26

申请号：US09116039

申请日：1998-07-15

申请人： Rahul Razdan ,  Richard E. Kessler ,  James B. Keller

发明人： Rahul Razdan ,  Richard E. Kessler ,  James B. Keller

IPC分类号： C06F1200

CPC分类号： G06F12/1054 ,  G06F12/0864 ,  G06F2212/1016 ,  G06F2212/655

摘要： A data caching system comprises a hashing function, a data store, a tag array, a page translator, a comparator and a duplicate tag array. The hashing function combines an index portion of a virtual address with a virtual page portion of the virtual address to form a cache index. The data store comprises a plurality of data blocks for holding data. The tag array comprises a plurality of tag entries corresponding to the data blocks, and both the data store and tag array are addressed with the cache index. The tag array provides a plurality of physical address tags corresponding to physical addresses of data resident within corresponding data blocks in the data store addressed by the cache index. The page translator translates a tag portion of the virtual address to a corresponding physical address tag. The comparator verifies a match between the physical address tag from the page translator and the plurality of physical address tags from the tag array, a match indicating that data addressed by the virtual address is resident within the data store. Finally, the duplicate tag array resolves synonym issues caused by hashing. The hashing function is such that addresses which are equivalent mod 213 are pseudo-randomly displaced within the cache. The preferred hashing function maps VA to bits of the cache index.

摘要翻译： 数据缓存系统包括散列函数，数据存储器，标签阵列，页面翻译器，比较器和重复的标签阵列。 散列函数将虚拟地址的索引部分与虚拟地址的虚拟页面部分组合以形成高速缓存索引。 数据存储器包括用于保存数据的多个数据块。 标签阵列包括与数据块相对应的多个标签条目，并且数据存储和标签阵列都用高速缓存索引寻址。 标签阵列提供与驻留在由高速缓存索引寻址的数据存储器中的相应数据块内的数据的物理地址相对应的多个物理地址标签。 页面翻译器将虚拟地址的标签部分转换为相应的物理地址标签。 比较器验证来自页面翻译器的物理地址标签与来自标签阵列的多个物理地址标签之间的匹配，指示由虚拟地址寻址的数据驻留在数据存储中的匹配。 最后，重复的标签数组解决哈希引起的同义词问题。 散列函数使得等效的mod 213的地址在高速缓存内被伪随机移位。 优先散列函数将VA <14,15异或13,12：6>映射到高速缓存索引的位<14：6>。

公开(公告)号：US06212493B1

公开(公告)日：2001-04-03

申请号：US09203119

申请日：1998-12-01

申请人： James D. Huggins ,  David H. Asher ,  James B. Keller

发明人： James D. Huggins ,  David H. Asher ,  James B. Keller

IPC分类号： G06F11263

CPC分类号： G06F11/263 ,  G06F11/2236

摘要： A technique for verification of a complex integrated circuit design, such as a microprocessor, using a randomly generated test program to simulate internal events and to determine the timing of external events. The simulation proceeds in two passes. During a first pass, the randomly generated test program and data vectors are applied to a simulation model of the design being verified. During this first pass, an internal agent collects profile data about internal events such as addresses and program counter contents as they occur. During a second pass of the process, the profile data is used to generate directed external events based upon the data observed during the first pass. In this manner, the advantages of rapid test vector generation provided through random schemes is achieved at the same time that a more directed external event correlation is accomplished.

摘要翻译： 用于验证诸如微处理器的复杂集成电路设计的技术，其使用随机生成的测试程序来模拟内部事件并确定外部事件的定时。 仿真进行两遍。 在第一次通过期间，将随机生成的测试程序和数据向量应用于被验证的设计的仿真模型。 在第一次通过期间，内部代理收集有关内部事件的配置文件数据，例如地址和程序计数器内容。 在该过程的第二次通过期间，轮廓数据用于基于在第一遍期间观察到的数据来生成定向的外部事件。 以这种方式，通过随机方案提供的快速测试向量生成的优点在实现更有针对性的外部事件相关性的同时实现。

公开(公告)号：US5029076A

公开(公告)日：1991-07-02

申请号：US512571

申请日：1990-04-09

申请人： Robert E. Stewart ,  James B. Keller

发明人： Robert E. Stewart ,  James B. Keller

IPC分类号： G06F13/364 ,  G06F13/40

CPC分类号： G06F13/4072 ,  G06F13/364

摘要： In a data processing system in which a plurality of data processing units or subsystems exchange logic signal groups by means of a system bus, apparatus is provided to allow sufficient time to permit transients on the system bus to decay, thereby increasing the integrity of the data. When the logic signal groups are applied to the system bus via conducting and nonconducting transistors, the presence of a logic signal on the system bus immediately prior to the application of a set of logic signals from a different data processing unit can delay the on-set of conduction of the most recently activated transistors, thereby resulting in transients of long duration. To accommodate these long transient conditions, the application of the new set of logic signals can be delayed until the transients on the system bus have been attenuated. Apparatus is disclosed for prohibiting access to the system bus by any subsystem during the system clock cycle following a subsystem access or by preventing access to the system bus by subsystems determined by the subsystem having access during the prior system clock cycle.

摘要翻译： 在其中多个数据处理单元或子系统通过系统总线交换逻辑信号组的数据处理系统中，提供设备以允许足够的时间来允许系统总线上的瞬变衰减，从而增加数据的完整性 。 当逻辑信号组通过导通和非导体晶体管施加到系统总线时，在应用来自不同数据处理单元的一组逻辑信号之前，系统总线上的逻辑信号的存在可以延迟设定 导致最近激活的晶体管的导通，从而导致长时间的瞬变。 为了适应这些长时间的瞬态条件，可以延迟新的逻辑信号集的应用，直到系统总线上的瞬变被衰减为止。 公开了用于在子系统访问之后的系统时钟周期期间禁止任何子系统访问系统总线的装置，或者通过由在先前系统时钟周期期间具有访问权限的子系统确定的子系统阻止对系统总线的访问。

公开(公告)号：US20140089647A1

公开(公告)日：2014-03-27

申请号：US13625382

申请日：2012-09-24

申请人： Ian D. Kountanis ,  Gerard R. Williams, III ,  James B. Keller

发明人： Ian D. Kountanis ,  Gerard R. Williams, III ,  James B. Keller

IPC分类号： G06F9/38

CPC分类号： G06F9/3842 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/38 ,  G06F9/3844 ,  G06F9/3848

摘要： In an embodiment, a processor may be configured to fetch N instruction bytes from an instruction cache (a “fetch group”), even if the fetch group crosses a cache line boundary. A branch predictor may be configured to produce branch predictions for up to M branches in the fetch group, where M is a maximum number of branches that may be included in the fetch group. In an embodiment, a branch direction predictor may be updated responsive to a misprediction and also responsive to the branch prediction being within a threshold of transitioning between predictions. To avoid a lookup to determine if the threshold update is to be performed, the branch predictor may detect the threshold update during prediction, and may transmit an indication with the branch.

摘要翻译： 在一个实施例中，处理器可以被配置为从指令高速缓存（“取出组”）获取N个指令字节，即使获取组跨越高速缓存行边界。 分支预测器可以被配置为在获取组中产生多达M个分支的分支预测，其中M是可以包括在获取组中的最大分支数。 在一个实施例中，分支方向预测器可以响应于错误预测而被更新，并且还响应于在预测之间的转换阈值内的分支预测。 为了避免查找以确定是否要执行阈值更新，分支预测器可以在预测期间检测阈值更新，并且可以用分支发送指示。

公开(公告)号：US08493863B2

公开(公告)日：2013-07-23

申请号：US13008184

申请日：2011-01-18

申请人： Gurjeet S. Saund ,  James B. Keller ,  Michael Frank

发明人： Gurjeet S. Saund ,  James B. Keller ,  Michael Frank

IPC分类号： H04L12/26

CPC分类号： H04L49/503 ,  H04L49/205

摘要： In an embodiment, one or more fabric control circuits may be inserted in a communication fabric to control various aspects of the communications by components in the system. The fabric control circuits may be included on the interface of the components to the communication fabric, in some embodiments. In other embodiments that include a hierarchical communication fabric, fabric control circuits may alternatively or additionally be included. The fabric control circuits may be programmable, and thus may provide the ability to tune the communication fabric to meet performance and/or functionality goals.

摘要翻译： 在一个实施例中，可以将一个或多个结构控制电路插入到通信结构中，以通过系统中的组件来控制通信的各个方面。 在一些实施例中，结构控制电路可以包括在组件的接口上到通信结构。 在包括分层通信结构的其他实施例中，结构控制电路可以可选地或另外包括。 织物控制电路可以是可编程的，因此可以提供调谐通信结构以满足性能和/或功能目标的能力。

公开(公告)号：US08078772B2

公开(公告)日：2011-12-13

申请号：US12908605

申请日：2010-10-20

申请人： James Wang ,  Zongjian Chen ,  James B. Keller

发明人： James Wang ,  Zongjian Chen ,  James B. Keller

IPC分类号： G06F13/00 ,  H03K5/135

CPC分类号： G06F5/14

摘要： In one embodiment, an apparatus comprises a first clocked storage device operable in a first clock domain corresponding to a first clock signal. The first clocked storage device has an input coupled to receive one or more bits transmitted on the input from a second clock domain corresponding to a second clock signal. The apparatus further comprises control circuitry configured to ensure that a change in a value of the one or more bits transmitted on the input meets setup and hold time requirements of the first clocked storage device. The control circuitry is responsive to a sample history of one of the first clock signal or the second clock signal to detect a phase relationship between the first clock signal and the second clock signal on each clock cycle to ensure the change meets the setup and hold time requirements.

公开(公告)号：US07124286B2

公开(公告)日：2006-10-17

申请号：US09824890

申请日：2001-04-02

申请人： Kevin J. McGrath ,  Michael T. Clark ,  James B. Keller

发明人： Kevin J. McGrath ,  Michael T. Clark ,  James B. Keller

IPC分类号： G06F9/30

CPC分类号： G06F9/30185 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/30112 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/342 ,  G06F9/45516

摘要： A processor supports a processing mode in which the address size is greater than 32 bits and the operand size may be 32 or 64 bits. The address size may be nominally indicated as 64 bits, although various embodiments of the processor may implement any address size which exceeds 32 bits, up to and including 64 bits, in the processing mode. The processing mode may be established by placing an enable indication in a control register into an enabled state and by setting a first operating mode indication and a second operating mode indication in a segment descriptor to predefined states. Other combinations of the first operating mode indication and the second operating mode indication may be used to provide compatibility modes for 32 bit and 16 bit processing compatible with the x86 processor architecture (with the enable indication remaining in the enabled state).

摘要翻译： 处理器支持地址大小大于32位的处理模式，操作数大小可以是32位或64位。 地址大小可以名义上表示为64位，尽管在处理模式下，处理器的各种实施例可以实现超过32位，高达并包括64位的任何地址大小。 可以通过将控制寄存器中的使能指示置于使能状态并且通过将段描述符中的第一操作模式指示和第二操作模式指示设置为预定状态来建立处理模式。 可以使用第一操作模式指示和第二操作模式指示的其他组合来提供与x86处理器架构兼容的32位和16位处理的兼容性模式（使能指示保持在使能状态）。

公开(公告)号：US06928500B1

公开(公告)日：2005-08-09

申请号：US08883118

申请日：1997-06-26

申请人： Raj Ramanujan ,  James B. Keller ,  William A. Samaras ,  John Derosa ,  Robert E. Stewart

发明人： Raj Ramanujan ,  James B. Keller ,  William A. Samaras ,  John Derosa ,  Robert E. Stewart

IPC分类号： G06F15/167 ,  G06F15/173 ,  H04L12/28 ,  H04L12/403 ,  G06F13/14 ,  G06F13/36

CPC分类号： H04L12/403 ,  G06F15/167 ,  G06F15/173 ,  H04L12/4625

摘要： A high speed bus system for use in a shared memory system that allows for the high speed transmissions of commands and data between a number of processors and a memory array of a multi-processor, shared memory system, with the high speed bus system including a central unit and a series of uni-directional buses that connect between the plurality of processors and shared memory, with the central unit including arbitration logic and a series of multiplexers to determine which CPUs are granted access to shared buses, scheduling logic that works with the arbitration logic and multiplexers to determine which CPUs are granted access to the shared buses, and port logic for combining the CPU transmissions and determining if such transmissions are valid.

摘要翻译： 一种用于共享存储器系统的高速总线系统，其允许多个处理器与多处理器共享存储器系统的存储器阵列之间的命令和数据的高速传输，其中高速总线系统包括 中央单元和连接在多个处理器和共享存储器之间的一系列单向总线，中央单元包括仲裁逻辑和一系列多路复用器，以确定哪些CPU被授权访问共享总线，调度逻辑与 仲裁逻辑和多路复用器，以确定哪些CPU被授权访问共享总线，以及端口逻辑，用于组合CPU传输并确定这些传输是否有效。