公开(公告)号：US5862075A

公开(公告)日：1999-01-19

申请号：US970445

申请日：1997-11-14

Applicant: Bruno Leconte ,  Alessandro Brigati ,  Jean Devin

Inventor： Bruno Leconte ,  Alessandro Brigati ,  Jean Devin

IPC: G11C16/10 ,  G11C16/22 ,  G11C16/04

CPC classification number: G11C16/22 ,  G11C16/10

Abstract: A FLASH memory is compatible with a standard EEPROM memory in terms of a write-by-page instruction with write protection. A circuit successively addresses one of the columns of a storage matrix in order to write a page previously stored in buffers, and the circuit addresses the writing of a protection bit after the writing of the page.

Abstract translation: 在具有写保护的逐页指令方面，FLASH存储器与标准EEPROM存储器兼容。 电路连续地寻址存储矩阵的列之一，以便写入先前存储在缓冲器中的页，并且该电路解决了写入页之后保护位的写入。

公开(公告)号：US5742546A

公开(公告)日：1998-04-21

申请号：US526500

申请日：1995-09-11

Applicant: Jean Devin

Inventor： Jean Devin

IPC: G11C11/413 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C7/00

CPC classification number: G11C8/08 ,  G11C8/10 ,  G11C8/18

Abstract: In a method for the decoding of the addresses of a memory, a pulse is generated at output of a filtering circuit at each change of address detected at the address bus to inhibit the address decoder during a determined duration. The filtering signal is applied more particularly to the row decoder which selects a row corresponding to an address applied to the input of the decoder and applies a control voltage to this row. This method is particularly advantageous in low-voltage memories.

Abstract translation: 在对存储器的地址进行解码的方法中，在地址总线检测到的地址的每个改变处，在滤波电路的输出处产生脉冲，以在确定的持续时间内禁止地址解码器。 滤波信号更具体地应用于行解码器，该行解码器选择与施加到解码器的输入端的地址相对应的行，并向该行施加控制电压。 该方法在低电压存储器中是特别有利的。

公开(公告)号：US5436479A

公开(公告)日：1995-07-25

申请号：US974429

申请日：1992-11-12

Applicant: Jean Devin

Inventor： Jean Devin

IPC: G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L29/68 ,  H01L29/78

CPC classification number: H01L29/7883 ,  G11C16/0425 ,  H01L29/42324

Abstract: A novel electrically programmable and erasable memory cell, comprising a single transistor, which is a floating gate transistor and has no selection transistor. Means are provided for establishing a high capacitive coupling between the drain and the floating gate. The capacitive coupling between the source and the floating gate is low, as is normally the case. Preferably, the control gate only partly covers the floating gate. Another part of the floating gate is covered by a semiconductor layer connected to the drain. It is the latter layer which establishes the high capacitive coupling according to the invention. Programming can then take place by the Fowler-Nordheim effect with the source under high impedance, i.e. without hot electron effect.

Abstract translation: 一种新颖的电可编程和可擦除存储单元，包括单晶体管，其为浮栅晶体管，并且不具有选择晶体管。 提供了用于在漏极和浮置栅极之间建立高电容耦合的装置。 源极和浮栅之间的电容耦合是低的，正如通常情况。 优选地，控制栅仅部分覆盖浮栅。 浮置栅极的另一部分由连接到漏极的半导体层覆盖。 建立根据本发明的高电容耦合的后一层。 然后可以通过Fowler-Nordheim效应在高阻抗下进行编程，即没有热电子效应。

公开(公告)号：US4964079A

公开(公告)日：1990-10-16

申请号：US342476

申请日：1989-04-24

Applicant: Jean Devin

Inventor： Jean Devin

IPC: G11C17/00 ,  G11C11/56 ,  G11C16/02

CPC classification number: G11C11/5621 ,  G11C11/5642

Abstract: The disclosure concerns electrically programmable memories and, notably, the memories known as EPROMs, EEPROMs, FLASH-EEPROMs. To increase the information storage capacity of a memory, it is proposed to define at least three (instead of two) sections of current coming from a cell to which reading voltages are applied. These sections correspond to n possible programmed states of the cell. Comparators define a piece of information stored, for example, in two-bit form on the outputs S1, S2. However, to ensure safety during the reading despite programming uncertainties, the cell is tested by means of additional comparators and, if the cell current measured for a programming level defined among n levels is too close to the current threshold that defines the programming threshold at this level, an operation for complementary programming of the cell is triggered.

Abstract translation: 本公开涉及电可编程存储器，特别是涉及称为EPROM，EEPROM，闪存EEPROM的存储器。 为了增加存储器的信息存储容量，建议定义来自应用了读取电压的单元的至少三个（而不是两个）电流。 这些部分对应于单元的n个可编程状态。 比较器定义在输出S1，S2上存储的例如以两位形式存储的信息。 然而，为了确保读取期间的安全性，尽管程序设计不确定，电池通过额外的比较器进行测试，如果为n个电平中定义的编程电平测量的电池电流太接近定义该编程阈值的当前阈值 级别，触发单元的互补编程操作。

公开(公告)号：US4958324A

公开(公告)日：1990-09-18

申请号：US269169

申请日：1988-11-09

Applicant: Jean Devin

Inventor： Jean Devin

IPC: G11C17/00 ,  G11C29/00 ,  G11C29/12 ,  G11C29/50

CPC classification number: G11C29/50 ,  G11C16/04 ,  G11C2029/5006

Abstract: A method for testing electrically programmable memories is disclosed. To enable the measurement of the current of programmed cells and blank cells (and not only to check whether the cells are programmed or not), and to enable this measurement even after the memory has been encapsulated in a package, it is proposed herein to connect, in testing mode, the bit line of a cell to be tested with the programming terminals to which there is applied, in programming mode, the programming high voltage Vpp. A low voltage Vte is applied to this terminal in testing mode, and the current flowing between this terminal and the voltage source is measured. This current is the current of the tested cell.

Abstract translation: 公开了一种用于测试电可编程存储器的方法。 为了能够测量编程的单元和空白单元的电流（并且不仅要检查单元是否被编程），并且即使在存储器被封装在封装中之后也能够进行该测量，因此在此建议连接 在测试模式下，在编程模式下编程高电压Vpp时，要应用要编程的端子进行测试的单元的位线。 在测试模式下，向该端子施加低电压Vte，并且测量在该端子与电压源之间流动的电流。 该电流是测试电池的电流。