公开(公告)号：US08008961B2

公开(公告)日：2011-08-30

申请号：US12637321

申请日：2009-12-14

申请人： Manish Garg ,  Chiaming Chai ,  Jeffrey Todd Bridges

发明人： Manish Garg ,  Chiaming Chai ,  Jeffrey Todd Bridges

IPC分类号： H03K3/00

CPC分类号： H03K3/0315 ,  H03K2005/00058 ,  H03K2005/00215

摘要： Adaptive clock generators, systems, and related methods than can be used to generate a clock signal for a functional circuit to avoid or reduce performance margin are disclosed. In certain embodiments, a clock generator autonomously and adaptively generates a clock signal according to a delay path(s) provided in a delay circuit(s) relating to a selected delay path(s) in the functional circuit(s). The clock generator includes a delay circuit(s) adapted to receive an input signal and delay the input signal by an amount relating to a delay path(s) of a functional circuit(s) to produce an output signal. A feedback circuit is coupled to the delay circuit(s) and responsive to the output signal, wherein the feedback circuit is adapted to generate the input signal back to the delay circuit(s) in an oscillation loop configuration. The input signal can be used to provide a clock signal to the functional circuit(s).

摘要翻译： 公开了可用于生成用于功能电路的时钟信号以避免或降低性能裕度的自适应时钟发生器，系统和相关方法。 在某些实施例中，时钟发生器根据在与功能电路中所选择的延迟路径相关的延迟电路中提供的延迟路径来自主地且自适应地生成时钟信号。 时钟发生器包括适于接收输入信号并将输入信号延迟与功能电路的延迟路径相关的量以产生输出信号的延迟电路。 反馈电路耦合到延迟电路并响应于输出信号，其中反馈电路适于在振荡环路配置中产生回到延迟电路的输入信号。 输入信号可用于向功能电路提供时钟信号。

公开(公告)号：US07821350B2

公开(公告)日：2010-10-26

申请号：US11624995

申请日：2007-01-19

申请人： Liang Dai ,  Brandon Wayne Lewis ,  Jeffrey Todd Bridges ,  Weihua Chen

发明人： Liang Dai ,  Brandon Wayne Lewis ,  Jeffrey Todd Bridges ,  Weihua Chen

IPC分类号： H03L7/04

CPC分类号： H03L7/189 ,  H03L2207/06

摘要： A phase-locked loop employing a plurality of oscillator complexes is disclosed. The phase-locked loop includes a clock output and a plurality of oscillator complexes operable to generate output signals. The phase-locked loop further includes control logic which is configured to selectively couple an output signal of one of the plurality of oscillator complexes to the clock output.

摘要翻译： 公开了一种采用多个振荡器复合器的锁相环。 锁相环包括时钟输出和可操作以产生输出信号的多个振荡器复合。 锁相环还包括控制逻辑，其被配置为选择性地将多个振荡器复合体之一的输出信号耦合到时钟输出。

公开(公告)号：US06055584A

公开(公告)日：2000-04-25

申请号：US975540

申请日：1997-11-20

申请人： Jeffrey Todd Bridges ,  Edward Hammond Green, III ,  Richard Gerard Hofmann ,  David Otero ,  Mark Michael Schaffer ,  Dennis Charles Wilkerson

发明人： Jeffrey Todd Bridges ,  Edward Hammond Green, III ,  Richard Gerard Hofmann ,  David Otero ,  Mark Michael Schaffer ,  Dennis Charles Wilkerson

IPC分类号： G06F13/28 ,  G06F12/00

CPC分类号： G06F13/28

摘要： A method and implementing system are provided which includes a DMA controller coupled to a slave bus controller through a processor local bus. The slave bus controller is also coupled to a memory unit. The memory unit is connected directly to a peripheral device. The DMA controller is arranged to receive a data transfer request from the peripheral unit and initiate a transfer cycle with the slave bus controller. The slave bus controller is selectively operable to assert a transfer signal to the memory unit which enables data movement directly between memory and the peripheral device in accordance with the request from the peripheral device. Upon completion of the address transfer and prior to the completion of the data transfer, the slave bus controller generates a transfer complete signal back to the peripheral device. This technique allows for a DMA FlyBy transfer to be overlapped with a subsequent processor local bus transfer.

摘要翻译： 提供了一种方法和实现系统，其包括通过处理器局部总线耦合到从总线控制器的DMA控制器。 从总线控制器还耦合到存储器单元。 存储器单元直接连接到外围设备。 DMA控制器被布置成从外围单元接收数据传输请求，并且与从总线控制器发起传输周期。 从总线控制器可选择性地操作以将传送信号断言到存储器单元，该存储器单元能够根据来自外围设备的请求直接在存储器和外围设备之间进行数据移动。 在地址传送完成之后，在完成数据传输之前，从总线控制器产生传输完成信号回外围设备。 这种技术允许DMA FlyBy传输与随后的处理器局部总线传输重叠。

公开(公告)号：US09483098B2

公开(公告)日：2016-11-01

申请号：US12752515

申请日：2010-04-01

申请人： Jeffrey Todd Bridges ,  Sanjay B. Patel

发明人： Jeffrey Todd Bridges ,  Sanjay B. Patel

IPC分类号： H02J3/14 ,  G06F1/30

CPC分类号： G06F1/305 ,  Y10T307/406

摘要： Circuits, systems, and methods for monitoring a power supply voltage and determining if the power supply voltage has drooped are disclosed. In one embodiment, a voltage monitoring circuit is provided and configured to determine if the power supply voltage supplied to a functional circuit has drooped. When no droop of the power supply voltage is detected, the voltage monitoring circuit is configured to provide an indication to the functional circuit to operate in a first mode. When droop of the power supply voltage is detected, the voltage monitoring circuit is configured to provide an indication to the functional circuit to operate in a second mode. In this manner, operating margin in the power supply may be reduced since the functional circuit may be configured to properly operate when a voltage droop of the power supply voltage occurs.

摘要翻译： 公开了用于监测电源电压并确定电源电压是否下降的电路，系统和方法。 在一个实施例中，电压监视电路被提供并且被配置为确定提供给功能电路的电源电压是否下垂。 当没有检测到电源电压下降时，电压监视电路被配置为向功能电路提供在第一模式下操作的指示。 当检测到电源电压下降时，电压监视电路被配置为向功能电路提供在第二模式中操作的指示。 以这种方式，由于功能电路可以被配置为在发生电源电压的电压下降时适当地操作，所以可以减少电源中的操作裕度。

公开(公告)号：US08725488B2

公开(公告)日：2014-05-13

申请号：US11828782

申请日：2007-07-26

申请人： Richard Gerard Hofmann ,  Jeffrey Todd Bridges

发明人： Richard Gerard Hofmann ,  Jeffrey Todd Bridges

IPC分类号： G06F9/455 ,  G06F1/26 ,  G06F1/32

CPC分类号： G06F1/324 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： Different software applications may use a set of instructions having critical timing paths less than a worst case critical timing path of a processor complex. For such applications, a supply voltage may be reduced while still maintaining the clock frequency necessary to meet the application's performance requirements. In order to reduce the supply voltage, an adaptive voltage scaling method is used. A critical path is selected from a plurality of critical paths for analysis on emulation logic to determine an attribute of the selected critical path during on chip functional operations. The selected critical path is representative of the worst case critical path to be in operation during a program execution. During on-chip functional operations, a voltage is controlled in response to the attribute, wherein the voltage supplies power to a power domain associated with the plurality of critical paths. The reduction in voltage reduces power drain based on instruction set usage allowing battery life to be extended.

摘要翻译： 不同的软件应用可以使用具有小于处理器复合体的最坏情况关键定时路径的关键定时路径的指令集。 对于这样的应用，可以降低电源电压，同时仍然保持满足应用的性能要求所需的时钟频率。 为了降低电源电压，使用自适应电压缩放方法。 从多个关键路径中选择关键路径用于分析仿真逻辑以在片上功能操作期间确定所选择的关键路径的属性。 所选择的关键路径代表在程序执行期间正在运行的最坏情况的关键路径。 在片上功能操作期间，响应于属性来控制电压，其中电压向与多个关键路径相关联的电力域提供电力。 降低电压可以根据指令集的使用量减少功耗，从而延长电池寿命。

公开(公告)号：US07805588B2

公开(公告)日：2010-09-28

申请号：US11254873

申请日：2005-10-20

申请人： Jeffrey Todd Bridges ,  James Norris Dieffenderfer ,  Thomas Sartorius ,  Brian Michael Stempel ,  Rodney Wayne Smith

发明人： Jeffrey Todd Bridges ,  James Norris Dieffenderfer ,  Thomas Sartorius ,  Brian Michael Stempel ,  Rodney Wayne Smith

IPC分类号： G06F12/00

CPC分类号： G06F12/1063 ,  G06F12/1054 ,  G06F12/145 ,  Y02D10/13

摘要： A processing system may include a memory configured to store data in a plurality of pages, a TLB, and a memory cache including a plurality of cache lines. Each page in the memory may include a plurality of lines of memory. The memory cache may permit, when a virtual address is presented to the cache, a matching cache line to be identified from the plurality of cache lines, the matching cache line having a matching address that matches the virtual address. The memory cache may be configured to permit one or more page attributes of a page located at the matching address to be retrieved from the memory cache and not from the TLB, by further storing in each one of the cache lines a page attribute of the line of data stored in the cache line.

摘要翻译： 处理系统可以包括被配置为在多个页面中存储数据的存储器，TLB和包括多个高速缓存行的存储器高速缓存。 存储器中的每个页面可以包括多行存储器。 当虚拟地址被呈现给高速缓存时，存储器高速缓存可以允许要从多条高速缓存行识别的匹配高速缓存行，匹配高速缓存行具有与虚拟地址匹配的匹配地址。 存储器高速缓存可以被配置为允许通过在高速缓存行的每一个中存储行的页面属性来允许位于匹配地址的页面的一个或多个页面属性从存储器高速缓存而不是从TLB检索， 的数据存储在缓存行中。

公开(公告)号：US20090031155A1

公开(公告)日：2009-01-29

申请号：US11828782

申请日：2007-07-26

申请人： Richard Gerard Hofmann ,  Jeffrey Todd Bridges

发明人： Richard Gerard Hofmann ,  Jeffrey Todd Bridges

IPC分类号： G06F1/32 ,  G06F1/26

CPC分类号： G06F1/324 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： Different software applications may use a set of instructions having critical timing paths less than a worst case critical timing path of a processor complex. For such applications, a supply voltage may be reduced while still maintaining the clock frequency necessary to meet the application's performance requirements. In order to reduce the supply voltage, an adaptive voltage scaling method is used. A critical path is selected from a plurality of critical paths for analysis on emulation logic to determine an attribute of the selected critical path during on chip functional operations. The selected critical path is representative of the worst case critical path to be in operation during a program execution. During on-chip functional operations, a voltage is controlled in response to the attribute, wherein the voltage supplies power to a power domain associated with the plurality of critical paths. The reduction in voltage reduces power drain based on instruction set usage allowing battery life to be extended.

摘要翻译： 不同的软件应用可以使用具有小于处理器复合体的最坏情况关键定时路径的关键定时路径的指令集。 对于这样的应用，可以降低电源电压，同时仍然保持满足应用的性能要求所需的时钟频率。 为了降低电源电压，使用自适应电压缩放方法。 从多个关键路径中选择关键路径用于分析仿真逻辑以在片上功能操作期间确定所选择的关键路径的属性。 所选择的关键路径代表在程序执行期间正在运行的最坏情况的关键路径。 在片上功能操作期间，响应于属性来控制电压，其中电压向与多个关键路径相关联的电力域提供电力。 基于指令集的使用，电压的降低可以减少功耗，从而延长电池寿命。

公开(公告)号：US07242600B2

公开(公告)日：2007-07-10

申请号：US11262062

申请日：2005-10-28

申请人： Michael ThaiThanh Phan ,  Chiaming Chai ,  Jeffrey Todd Bridges ,  Jeffrey Herbert Fischer

发明人： Michael ThaiThanh Phan ,  Chiaming Chai ,  Jeffrey Todd Bridges ,  Jeffrey Herbert Fischer

IPC分类号： G11C15/00

CPC分类号： G11C15/00 ,  G11C8/12 ,  G11C15/04

摘要： A CAM bank is functionally divided into two or more sub-banks, without replicating CAM driver circuits, by disabling all match line discharge circuits in the bank, and selectively enabling the discharge circuits in entries comprising sub-banks. At least one selectively actuated switching circuit is interposed between the virtual ground node of each discharging comparator in the discharge circuit of a sub-bank and circuit ground. When the switching circuit is in a non-conductive state, the virtual ground node is maintained at a voltage level sufficiently above circuit ground to preclude discharging a connected match line within the CAM access time. When the switching circuit is placed in a conductive state, the virtual ground node is pulled to circuit ground and the connected match line may be discharged by a miscompare. Control signals, which may be decoded from address bits, are distributed to the switching circuits to define the CAM sub-banks.

摘要翻译： CAM组在功能上划分为两个或更多个子行，不复制CAM驱动电路，禁止该组中的所有匹配线放电电路，并且选择性地使得放电电路在包含子行的条目中使能。 至少一个选择性致动的切换电路插入在子组的放电电路中的每个放电比较器的虚拟接地节点和电路接地之间。 当开关电路处于非导通状态时，虚拟接地节点保持在足够高于电路接地的电压电平，以防止在CAM访问时间内放电连接的匹配线。 当开关电路处于导通状态时，虚拟接地节点被拉到电路接地，并且连接的匹配线可能被误比较地放电。 可以从地址位解码的控制信号被分配给切换电路以定义CAM子库。

公开(公告)号：US09128720B2

公开(公告)日：2015-09-08

申请号：US13183129

申请日：2011-07-14

申请人： Gerald Paul Michalak ,  Jeffrey Todd Bridges

发明人： Gerald Paul Michalak ,  Jeffrey Todd Bridges

IPC分类号： G06F1/00 ,  G06F1/32 ,  G06F1/26

CPC分类号： G06F1/3296 ,  G06F1/26 ,  Y02D10/172

摘要： Methods and apparatus for voltage scaling are provided. In an example, an operational limit of a processor is determined by varying a supply voltage to force a processor interrupt fault and/or a processor reset. A clock frequency and the supply voltage can be maintained substantially constant for a time duration. If these operational parameters do not force the processor interrupt fault and/or the processor reset, the supply voltage is varied again, and the clock frequency and the supply voltage are maintained substantially constant for a second time duration. The variation continues until initiation of the processor interrupt fault and/or the processor reset, at which time least one of a clock frequency, the supply voltage, and a temperature are recorded as an operational limit. After determining the operational limit, the supply voltage is adjusted to within the operational limit.

摘要翻译： 提供了电压缩放的方法和装置。 在一个示例中，通过改变供电电压来强制处理器中断故障和/或处理器复位来确定处理器的操作限制。 时钟频率和电源电压可以在一段持续时间内保持基本上恒定。 如果这些操作参数不强制处理器中断故障和/或处理器复位，则电源电压再次变化，并且时钟频率和电源电压在第二持续时间内保持基本上恒定。 变化继续，直到处理器中断故障开始和/或处理器复位，此时将时钟频率，电源电压和温度中的至少一个记录为操作限制。 确定运行极限后，将电源电压调整到运行极限内。

公开(公告)号：US20110241423A1

公开(公告)日：2011-10-06

申请号：US12752515

申请日：2010-04-01

申请人： Jeffrey Todd Bridges ,  Sanjay B. Patel

发明人： Jeffrey Todd Bridges ,  Sanjay B. Patel

IPC分类号： H02J1/00

CPC分类号： G06F1/305 ,  Y10T307/406

摘要： Circuits, systems, and methods for monitoring a power supply voltage and determining if the power supply voltage has drooped are disclosed. In one embodiment, a voltage monitoring circuit is provided and configured to determine if the power supply voltage supplied to a functional circuit has drooped. When no droop of the power supply voltage is detected, the voltage monitoring circuit is configured to provide an indication to the functional circuit to operate in a first mode. When droop of the power supply voltage is detected, the voltage monitoring circuit is configured to provide an indication to the functional circuit to operate in a second mode. In this manner, operating margin in the power supply may be reduced since the functional circuit may be configured to properly operate when a voltage droop of the power supply voltage occurs.

摘要翻译： 公开了用于监测电源电压并确定电源电压是否下降的电路，系统和方法。 在一个实施例中，电压监视电路被提供并且被配置为确定提供给功能电路的电源电压是否下垂。 当没有检测到电源电压下降时，电压监视电路被配置为向功能电路提供在第一模式下操作的指示。 当检测到电源电压下降时，电压监视电路被配置为向功能电路提供在第二模式中操作的指示。 以这种方式，由于功能电路可以被配置为在发生电源电压的电压下降时适当地操作，所以可以减少电源中的操作裕度。