公开(公告)号：US09543965B1

公开(公告)日：2017-01-10

申请号：US14046467

申请日：2013-10-04

申请人： Altera Corporation

发明人： Weiqi Ding

IPC分类号： G11C8/18 ,  H03L7/04 ,  G11C5/06 ,  G06F1/10

CPC分类号： H03L7/04 ,  G06F1/10 ,  G11C5/06 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1243 ,  H03K3/0315

摘要： An integrated circuit package includes an interposer with an embedded clock network formed by multiple clock trees. A die with first and second clock circuits is disposed over the interposer. At least one of the first and second clock trees is a resonant clock tree and both the first and second clock circuits may provide clock signals at different frequencies. The first clock circuit may provide clock signals at one frequency to a clock tree in the embedded clock network while the second clock circuit may provide clock signals at another frequency to another clock tree in the embedded clock tree network.

摘要翻译： 集成电路封装包括具有由多个时钟树形成的嵌入式时钟网络的插入器。 具有第一和第二时钟电路的管芯设置在插入件上。 第一和第二时钟树中的至少一个是谐振时钟树，并且第一和第二时钟电路都可以提供不同频率的时钟信号。 第一时钟电路可以以一个频率将时钟信号提供给嵌入式时钟网络中的时钟树，而第二时钟电路可以以另一个频率向嵌入式时钟树网络中的另一个时钟树提供时钟信号。

公开(公告)号：US08228126B2

公开(公告)日：2012-07-24

申请号：US12104608

申请日：2008-04-17

申请人： Che-Fu Liang ,  Sy-Chyuan Hwu ,  Shen-Iuan Liu

发明人： Che-Fu Liang ,  Sy-Chyuan Hwu ,  Shen-Iuan Liu

IPC分类号： H03L7/085 ,  H03L7/089 ,  H03L7/04

CPC分类号： H04L7/033 ,  H03L7/0805 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/18

摘要： A clock and data recovery circuit is disclosed and comprises a gated voltage-controlled oscillator (GVCO), a PLL unit, a phase-controlled frequency divider, a multiplexer, a matching circuit and a double-edge-triggered D flip-flop (DDFF). The GVCO receives a data signal and a reference voltage to generate first and second clock signals. The PLL unit receives a reference clock signal and generates the reference voltage to adjust the first and second clock signals at the vicinity of the predetermined frequency. The phase-controlled frequency divider receives and divides the first clock signal by N to output a third clock signal. The multiplexer controlled by a selection signal receives and outputs the second or the third clock signal. The matching circuit receives the data signal and the selection signal to match the delays therebetween. The DDFF receives the output signals from the matching circuit and the multiplexer, and outputs a recovered data signal.

摘要翻译： 公开了一种时钟和数据恢复电路，包括门控压控振荡器（GVCO），PLL单元，相位控制分频器，多路复用器，匹配电路和双边沿触发D触发器（DDFF ）。 GVCO接收数据信号和参考电压以产生第一和第二时钟信号。 PLL单元接收参考时钟信号并产生参考电压以调整在预定频率附近的第一和第二时钟信号。 相控分频器接收并将第一时钟信号除以N以输出第三时钟信号。 由选择信号控制的多路复用器接收并输出第二或第三时钟信号。 匹配电路接收数据信号和选择信号以匹配它们之间的延迟。 DDFF从匹配电路和多路复用器接收输出信号，并输出恢复的数据信号。

公开(公告)号：US07821350B2

公开(公告)日：2010-10-26

申请号：US11624995

申请日：2007-01-19

申请人： Liang Dai ,  Brandon Wayne Lewis ,  Jeffrey Todd Bridges ,  Weihua Chen

发明人： Liang Dai ,  Brandon Wayne Lewis ,  Jeffrey Todd Bridges ,  Weihua Chen

IPC分类号： H03L7/04

CPC分类号： H03L7/189 ,  H03L2207/06

摘要： A phase-locked loop employing a plurality of oscillator complexes is disclosed. The phase-locked loop includes a clock output and a plurality of oscillator complexes operable to generate output signals. The phase-locked loop further includes control logic which is configured to selectively couple an output signal of one of the plurality of oscillator complexes to the clock output.

摘要翻译： 公开了一种采用多个振荡器复合器的锁相环。 锁相环包括时钟输出和可操作以产生输出信号的多个振荡器复合。 锁相环还包括控制逻辑，其被配置为选择性地将多个振荡器复合体之一的输出信号耦合到时钟输出。

公开(公告)号：US5781847A

公开(公告)日：1998-07-14

申请号：US526025

申请日：1995-09-08

申请人： Ian M. Clarke ,  Stuart M. Feeney

发明人： Ian M. Clarke ,  Stuart M. Feeney

IPC分类号： H04N7/20 ,  H03L7/04 ,  H03L7/06 ,  H03L7/14 ,  H04B1/04 ,  H04B1/00

CPC分类号： H03L7/141 ,  H03L7/04

摘要： In multiple-channel microwave transmitters and communications systems, such as multi-point video distribution systems operating at frequencies of around 29 GHz or 40 GHz, good frequency stability for each of the channel frequencies is achieved with a feed-back loop including an error detector circuit. The error detector circuit (39,29) is coupled between a sampler and an input circuit of the source. This detector circuit detects any drift or other error in the carrier frequency of the sample from the desired microwave frequency for that channel signal and provides a corrective signal to the input circuit. The part of the feed-back loop comprising at least a part of the detector circuit is common to a group of the channels. Switch means couple the common part of the feed-back loop between the sampler and the source input circuit of each channel, and so permit this common part to be time multiplexed between the respective feed-back loops of the group of channels. The input circuit for each source applies an up-datable bias signal for regulating the frequency of the source in accordance with the last corrective signal generated by the detector circuit for that source. By adopting such a stabilisation arrangement in accordance with the present invention, expensive component parts of the feed-back loop can be common to a group of the channels, so reducing the assembly cost of the multiple-channel transmitter. Good long-term frequency stability for all the channels can be obtained, including a reliably constant frequency relationship between the channels.

摘要翻译： 在多通道微波发射器和通信系统中，例如在大约29GHz或40GHz的频率下操作的多点视频分配系统，通过包括误差检测器的反馈回路来实现每个通道频率的良好的频率稳定性 电路。 误差检测器电路（39,29）耦合在采样器和源的输入电路之间。 该检测器电路从该通道信号的期望的微波频率检测样品的载波频率中的任何漂移或其他误差，并向输入电路提供校正信号。 包括检测器电路的至少一部分的反馈回路的部分对于一组通道是共同的。 开关意味着将每个通道的采样器和源输入电路之间的反馈回路的公共部分耦合，因此允许这个公共部分在通道组的各个反馈回路之间进行时间复用。 每个源的输入电路根据由该源的检测器电路产生的最后一个校正信号施加可调节偏置信号，用于调节源的频率。 通过采用根据本发明的这种稳定装置，反馈回路的昂贵组件可以是一组通道共同的，因此降低了多通道发射机的组装成本。 可以获得所有通道的良好的长期频率稳定性，包括通道之间可靠恒定的频率关系。

公开(公告)号：US5294895A

公开(公告)日：1994-03-15

申请号：US954727

申请日：1992-09-30

申请人： Stuart M. Feeney ,  David H. Evans ,  Kenneth Holford

发明人： Stuart M. Feeney ,  David H. Evans ,  Kenneth Holford

IPC分类号： H01P1/00 ,  H01P7/06 ,  H03B5/18 ,  H03B9/12 ,  H03B9/14 ,  H03L7/04 ,  H03L7/06 ,  H03B7/14

CPC分类号： H03L7/04 ,  H03B9/141 ,  H03B2009/126

摘要： In addition to a first opening (11) forming a primary output from a waveguide cavity (10) of a microwave oscillator, a coupling aperture (12) in a reflective wall (32) provides a secondary output which does not degrade the performance or tuning characteristics of the source. Less than -20 dB of the source power may be coupled out via the aperture (12) and is used in a feed-back loop (12,21,23,24,36) with an harmonic mixer (21) and frequency discriminator (24) to stabilize the source. The mixer comprises a further waveguide section (15) separated from the source cavity (10) by the reflective wall (32). An advantageous mixer assembly comprises a circuit substrate which is mounted across the further waveguide cavity (15) and which carries an inductive probe by which the signal from the coupling aperture (12) is fed to an antiparallel pair of mixer diodes on the substrate. The whole assembly may be bolted together through holes (34).

摘要翻译： 除了形成来自微波振荡器的波导腔（10）的初级输出的第一开口（11）之外，反射壁（32）中的耦合孔（12）提供不会降低性能或调谐的次级输出 来源的特点。 小于-20dB的源功率可以经由孔径（12）耦合出来，并且用于具有谐波混频器（21）和鉴频器（12,21,23,24,36）的反馈回路（12,21,23,24,36） 24）稳定源。 混合器包括通过反射壁（32）与源腔（10）分离的另外的波导部分（15）。 有利的混合器组件包括安装在另外的波导腔（15）上并且承载感应探针的电路衬底，通过该电感探针将耦合孔（12）的信号馈送到衬底上的反平行的一对混合二极管。 整个组件可以通过孔（34）螺栓连接在一起。

公开(公告)号：US5220292A

公开(公告)日：1993-06-15

申请号：US815981

申请日：1992-01-02

申请人： Michael J. Bianchini ,  Richard A. Michalik ,  John A. Chiesa ,  Joanne Mistler

发明人： Michael J. Bianchini ,  Richard A. Michalik ,  John A. Chiesa ,  Joanne Mistler

IPC分类号： H03B5/00 ,  H03L7/04 ,  H03L7/06

CPC分类号： H03L7/04

摘要： A microwave oscillator is shown to include an oscillator having an output and a control port and a feedback circuit disposed between the output and the control port of the oscillator. The feedback circuit includes a modulated laser, having an input and an output, the input responsive to a portion of a signal from the output of the oscillator and a photo detector having an input and an output, the input of the photo detector responsive to a signal from the output of the modulated laser delayed by a predetermined amount of time. The feedback circuit further includes a detector having a first and a second input and an output, the first input of the detector responsive to a signal from the output of the photo detector, the second input responsive to a portion of the signal from the output of the oscillator shifted in phase to be in phase quadrature with the signal at the first input of the detector and the output of the detector coupled to the control port of the oscillator. With such an arrangement, a microwave oscillator having improved FM noise performance than known microwave oscillators is provided.

公开(公告)号：US5036299A

公开(公告)日：1991-07-30

申请号：US541968

申请日：1990-06-22

申请人： G. John Dick ,  Jonathan E. Saunders

发明人： G. John Dick ,  Jonathan E. Saunders

IPC分类号： H03B1/04 ,  H03B5/18 ,  H03L7/04

CPC分类号： H03L7/04 ,  H03B5/1864 ,  H03B2200/0088 ,  H03B2202/076

摘要： Microwave oscilltors incorporate r.f. feedback with carrier suppression to reduce phase noise. In a direct feedback oscillator arrngement a circulator is interposed between the r.f. amplifier and the high-Q resonator. The amplifier output is applied to the slightly over-coupled input port of the resonator so that the resultant net return signal is the vectorial difference between the signals emitted and reflected from the resonator. The gain of the r.f. amplifier is chosen to regenerate the forward signal from the net return signal. In a STALO-type arrangement, the resonator is critically coupled and an r.f. amplifier added to the path of the net return signal. The sensitivity of the STALO-type feedback loop is thereby enhanced while added amplifier noise is minimized by the superposition of the signals emitted by and reflected from the resonator.

摘要翻译： 微波振荡器包含r.f. 具有载波抑制的反馈以减少相位噪声。 在直接反馈振荡器中，循环器介于r.f.之间。 放大器和高Q谐振器。 放大器输出被施加到谐振器的稍微过耦合的输入端口，使得所得到的净返回信号是从谐振器发射和反射的信号之间的矢量差。 r.f.的收益 选择放大器以从净返回信号再生正向信号。 在STALO型布置中，谐振器被严格耦合，并且r.f. 放大器添加到净返回信号的路径。 由此增强了STALO型反馈环路的灵敏度，同时通过由共振器发射和反射的信号的叠加来使附加的放大器噪声最小化。

公开(公告)号：US4388537A

公开(公告)日：1983-06-14

申请号：US212520

申请日：1980-12-03

申请人： Akira Kanuma

发明人： Akira Kanuma

IPC分类号： H01L27/04 ,  G05F3/20 ,  G11C11/408 ,  H01L21/822 ,  H01L29/78 ,  H03B5/24 ,  H03L7/04

CPC分类号： G05F3/205

摘要： Disclosed is a substrate bias generator circuit which comprises an oscillator circuit, a driving circuit producing a rectangular-wave signal in accordance with an oscillation output signal from the oscillator circuit, and a charge pump circuit pumping electric charges into a substrate in accordance with the rectangular-wave output signal from the driving circuit. The oscillator circuit is a voltage-controlled oscillator circuit whose oscillation frequency is controlled in accordance with a substrate bias voltage from the charge pump circuit.

摘要翻译： 公开了一种衬底偏置发生器电路，其包括振荡器电路，根据来自振荡器电路的振荡输出信号产生矩形波信号的驱动电路，以及电荷泵电路，将电荷根据矩形 来自驱动电路的波输出信号。 振荡电路是一个压控振荡器电路，其振荡频率根据来自电荷泵电路的衬底偏置电压来控制。

公开(公告)号：US4316108A

公开(公告)日：1982-02-16

申请号：US78906

申请日：1979-09-25

申请人： Walter M. Rogers, Jr.

发明人： Walter M. Rogers, Jr.

IPC分类号： H03D3/00 ,  H03J7/08 ,  H03L7/04

CPC分类号： H03J7/08 ,  H03D3/005

摘要： A tracking filter suitable for use in the IF stage of FM receiver circuitry incorporates a bandpass filter the components of which yield a characteristic that permits the filter to provide substantially the entirety of a required 90.degree. phase shift for phase detection control circuitry that rapidly actively tunes capacitive components of the filter without imparting unacceptable group delay behavior to the configuration. The filter is a two-pole pair, single zero at the orgin, bandpass filter inserted in the signal path between a pair of signal power splitters. Part of the input signal is applied from the first splitter to one input of a phase comparator the other input of which is derived from the output signal via the second power splitter. The output of the phase comparator is applied through a broadband control amplifier to actively adjust the center frequency of the bandpass filter. Advantageously, this configuration enables the filter to have its center frequency effectively coincide with the instantaneous frequency of the deviating input signal, whereby an increase in performance over conventional filter approaches is obtained.

摘要翻译： 适用于FM接收器电路的IF级的跟踪滤波器包括带通滤波器，其组件产生允许滤波器基本上为快速主动调谐的相位检测控制电路提供所需的90°相位的整体的特性 滤波器的电容分量，而不会对组态造成不可接受的组延迟行为。 滤波器是两极对，在原始的带通滤波器中单个零插入一对信号功率分配器之间的信号路径中。 输入信号的一部分从第一分离器施加到相位比较器的一个输入，相位比较器的另一个输入通过第二功率分配器从输出信号导出。 相位比较器的输出通过宽带控制放大器进行，主动调整带通滤波器的中心频率。 有利的是，该配置使得滤波器的中心频率与偏移输入信号的瞬时频率有效地一致，从而获得了超过常规滤波器方法的性能的提高。

公开(公告)号：US4217552A

公开(公告)日：1980-08-12

申请号：US942531

申请日：1978-09-15

申请人： Takao Mogi ,  Koji Morita ,  Hisao Okada

发明人： Takao Mogi ,  Koji Morita ,  Hisao Okada

IPC分类号： H03J7/18 ,  H03J5/02 ,  H03J7/02 ,  H03J7/06 ,  H03J7/28 ,  H03L7/04 ,  H03L7/181 ,  H04N5/44 ,  H04N5/50 ,  H04B1/32

CPC分类号： H03J7/06 ,  H03J5/0263 ,  H03L7/04

摘要： A digital tuning receiver having an electrically tuneable tuner and an AFT circuit is driven in a unidirectional sweep by the D/A converted output of a reversible counter. The reversible counter continues to count input pulses, and the unidirectional sweep continues until stopped by the reception of a signal which produces a first signal from an AFT frequency discriminator followed within a predetermined time by a second signal of opposite polarity from the AFT frequency discriminator. The number stored in the stopped reversible counter may be further adjusted by AFT signals and stored for later recall. If the second signal is not received within a predetermined time, as occurs with spurious beat signals, the sweep is not stopped but continues until a proper signal is received.

摘要翻译： 具有电可调谐调谐器和AFT电路的数字调谐接收机通过可逆计数器的D / A转换输出在单向扫描中被驱动。 可逆计数器继续对输入脉冲进行计数，并且通过接收从AFT鉴频器产生来自AFT鉴频器的相反极性的第二信号的预定时间产生第一信号的信号，继续直到停止单向扫描。 可以通过AFT信号进一步调整存储在停止的可逆计数器中的数量，并存储以备以后调用。 如果在预定时间内没有接收到第二信号，如同假跳跃信号一样，扫描不停止，直到接收到适当的信号为止。