摘要:
A method of patterning an integrated circuit including generating a thermal profile of a reticle is provided. The thermal profile of the reticle may illustrate heat accumulation (e.g., a temperature) in a EUV reticle due an incident EUV radiation beam. The thermal profile may be determined using the pattern density of the reticle. The reticle is irradiated with a radiation beam having an extreme ultraviolet (EUV) wavelength. A thermal control profile may be generated using the thermal profile, which may define a parameter of the lithography process such as, a temperature gradient of a thermal control chuck. The thermal control profile may be downloaded to the EUV lithography tool (e.g., scanner or stepper) for use in a process. A separate thermal control profile may be provided for different reticles.
摘要:
A method and system for fabricating a substrate is disclosed. First, a plurality of process chambers are provided, at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate and at least one of the plurality of process chambers containing a plasma filtering plate library. A plasma filtering plate is selected and removed from the plasma filtering plate library. Then, the plasma filtering plate is inserted into at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate. Subsequently, an etching process is performed in the substrate.
摘要:
The present disclosure relates to a lithographic tool arrangement for semiconductor workpiece processing. The lithographic tool arrangement groups lithographic tools into clusters, and selectively transfers a semiconductor workpiece between a plurality of lithographic tools of a first type in a first cluster to a plurality of lithographic tools of a second type in a second cluster. The selective transfer is achieved though a transfer assembly, which is coupled to a defect scan tool that identifies defects generated in the lithographic tool of the first type. The disclosed lithographic tool arrangement also utilizes shared structural elements such as a housing assembly, and shared functional elements such as gases and chemicals. The lithographic tool arrangement may consist of baking, coating, exposure, and development units configured to provide a modularization of these various components in order to optimize throughput and efficiency for a given lithographic fabrication process.
摘要:
A method of manufacturing a photomask is described. The graphic data of the photomask are provided, and than an optical proximity correction is performed to the graphic data. A process rule check is then performed to the graphic data with the optical proximity correction. When at least one failed pattern not passing the process rule check is found in the graphic data, a repair procedure is performed only to the failed pattern so that the failed pattern can pass the process rule check. The patterns of the photomask are then formed according to the corrected and repaired graphic data.
摘要:
A dual wavelength exposure system provides for patterning a resist layer formed on a wafer for forming semiconductor devices, using two exposure operations, one including a first radiation having a first wavelength and the other including a second radiation including a second wavelength. Different or the same lithography tool may be used to generate the first and second radiation. For each die formed on the semiconductor device, a critical portion of the pattern is exposed using a first exposure operation that uses a first radiation with a first wavelength and a non-critical portion of the pattern is exposed using a second exposure operation utilizing the second radiation at a second wavelength. The resist material is chosen to be sensitive to both the first radiation having a first wavelength and the second radiation having the second wavelength.
摘要:
In accordance with the present invention, a method for forming a via-first dual damascene interconnect structure by using gap-filling material whose thickness is easily controlled by a developer is provided. The essential part of the present invention is the application of gap-filling materials such as novolak, PHS, acrylate, methacrylate, and COMA to fill vias. Filling vias with these materials can get a greater planar topography for trench patterning due to its excellent gap-filling capacity, protect the bottom of vias from damage during the trench etch, and prevent the fence problem by using a developer to control its thickness in vias.