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210 条记录 (耗时 0.026 秒)

    Method and apparatus for protecting a circuit during a hot socket condition
    41.
    发明申请
    Method and apparatus for protecting a circuit during a hot socket condition 有权
    在热插座状态下保护电路的方法和装置

    公开(公告)号：US20070115028A1

    公开(公告)日：2007-05-24

    申请号：US11251099

    申请日：2005-10-14

    申请人： Xiaobao Wang ,  Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang

    发明人： Xiaobao Wang ,  Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang

    IPC分类号： H03K19/00

    CPC分类号： H03K19/00315

    摘要： The hot socket detect circuit of the present invention includes a well bias circuit and three hot socket detect blocks. If the output of any of the three hot socket detect blocks is a digital high signal then the output of the hot socket detect circuit is a digital high signal. The digital high signal indicates that a hot socket condition exists.

    摘要翻译： 本发明的热插座检测电路包括阱偏置电路和三个热插座检测块。 如果三个热插座检测块中的任一个的输出是数字高信号，则热插座检测电路的输出是数字高电平信号。 数字高电平信号表示存在热插座状况。

    Programmable on-chip differential termination impedance
    42.
    发明授权
    Programmable on-chip differential termination impedance 有权
    可编程片上差分终端阻抗

    公开(公告)号：US07205788B1

    公开(公告)日：2007-04-17

    申请号：US11086979

    申请日：2005-03-21

    申请人： Bonnie I. Wang ,  Chiakang Sung ,  Khai Nguyen

    发明人： Bonnie I. Wang ,  Chiakang Sung ,  Khai Nguyen

    IPC分类号： H03K19/003

    CPC分类号： H04L25/0278

    摘要： The circuits and methods are provided for impedance termination on an integrated circuit. A network of resistors are formed on an integrated circuit (IC) to provide on-chip impedance termination to differential input/output (IO) pins. Transistors are coupled in the network of termination resistors. The transistors provide additional termination impedance to the differential IO pins. The transistors can be turned ON or OFF separately to change the impedance termination.

    摘要翻译： 电路和方法用于集成电路上的阻抗终端。 在集成电路（IC）上形成电阻网络，为差分输入/输出（IO）引脚提供片内阻抗终端。 晶体管耦合在终端电阻网络中。 晶体管为差分IO引脚提供额外的终端阻抗。 晶体管可以单独打开或关闭，以改变阻抗终止。

    Differential input buffers with elevated power supplies
    44.
    发明授权
    Differential input buffers with elevated power supplies 有权
    带升压电源的差分输入缓冲器

    公开(公告)号：US07046037B1

    公开(公告)日：2006-05-16

    申请号：US11153676

    申请日：2005-06-15

    申请人： Jeffrey Tyhach ,  Bonnie Wang ,  Chiakang Sung ,  Khai Nguyen

    发明人： Jeffrey Tyhach ,  Bonnie Wang ,  Chiakang Sung ,  Khai Nguyen

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/018528 ,  H03K17/04106 ,  H04L25/0272 ,  H04L25/0292

    摘要： Input buffer circuitry for handling high-speed differential input signals on an integrated circuit is provided. The input buffer circuitry may use two parallel differential input buffers with overlapping input-voltage ranges. Logic on the integrated circuit may be powered at a core-logic power supply voltage. Input-output circuitry on the integrated circuit may be powered at an input-output voltage level. To improve the performance of the input buffers in the overlap range, at least one the input buffers can be powered using a total power supply voltage drop that exceeds the core-logic power supply level. One of the input buffers may be configured to handle lower-voltage input signals. This input buffer may be powered using the input-output power supply level.

    摘要翻译： 提供了用于处理集成电路中的高速差分输入信号的输入缓冲电路。 输入缓冲器电路可以使用具有重叠输入电压范围的两个并行差分输入缓冲器。 集成电路上的逻辑可以以核心逻辑电源电压供电。 集成电路上的输入输出电路可以以输入 - 输出电压电平供电。 为了在重叠范围内提高输入缓冲器的性能，可以使用超过核心逻辑电源电平的总电源电压降供电至少一个输入缓冲器。 其中一个输入缓冲器可被配置为处理较低电压的输入信号。 该输入缓冲器可以使用输入 - 输出电源电平供电。

    Programmable I/O element circuit for high speed logic devices
    46.
    发明申请
    Programmable I/O element circuit for high speed logic devices 有权
    用于高速逻辑器件的可编程I / O元件电路

    公开(公告)号：US20050162187A1

    公开(公告)日：2005-07-28

    申请号：US11025774

    申请日：2004-12-29

    申请人： Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang ,  Joseph Huang ,  Phillip Pan ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Xiaobao Wang ,  Tzung-Chin Chang

    发明人： Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang ,  Joseph Huang ,  Phillip Pan ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Xiaobao Wang ,  Tzung-Chin Chang

    IPC分类号： C07K14/47 ,  C07K16/28 ,  H03K19/177

    CPC分类号： C07K16/28 ,  A61K2039/505 ,  C07K14/47

    摘要： A programmable I/O element for an I/O terminal of a logic array is suitable for operating according to high speed I/O modes such as double data rate and zero bus turnaround. The I/O element may include an input block with two registers for registering input signals from the terminal upon alternate clock edges. In addition or alternatively, it may include an output block with two registers that separately register output signals from the array on the same clock edge and a multiplexer that alternately outputs those signals. For bidirectional terminals, the multiplexer output is connectable to the I/O terminal via an output buffer, and an output enable block provides an enable signal to a gating input of the output buffer. Programmable delays may be included in the input, output, and output enable paths, in particular to provide a slower turn-on time than turn-off time for the output buffer.

    摘要翻译： 用于逻辑阵列的I / O端子的可编程I / O元件适用于根据双速数据速率和零总线周转等高速I / O模式进行工作。 I / O元件可以包括具有两个寄存器的输入块，用于在备用时钟边缘上从终端注册输入信号。 另外或替代地，它可以包括具有两个寄存器的输出块，该两个寄存器在相同的时钟沿上单独地寄存来自阵列的输出信号，以及交替地输出这些信号的多路复用器。 对于双向端子，多路复用器输出可通过输出缓冲器连接到I / O端子，并且输出使能块为输出缓冲器的选通输入提供使能信号。 可编程延迟可以包括在输入，输出和输出使能路径中，特别是提供比输出缓冲器的关断时间更慢的导通时间。

    Programmable on-chip differential termination impedance
    47.
    发明授权
    Programmable on-chip differential termination impedance 有权
    可编程片上差分终端阻抗

    公开(公告)号：US06888369B1

    公开(公告)日：2005-05-03

    申请号：US10622314

    申请日：2003-07-17

    申请人： Bonnie I. Wang ,  Chiakang Sung ,  Khai Nguyen

    发明人： Bonnie I. Wang ,  Chiakang Sung ,  Khai Nguyen

    IPC分类号： H03K19/003 ,  H04L25/02

    CPC分类号： H04L25/0278

    摘要： The circuits and methods are provided for impedance termination on an integrated circuit. A network of resistors are formed on an integrated circuit (IC) to provide on-chip impedance termination to differential input/output (IO) pins. Transistors are coupled in the network of termination resistors. The transistors provide additional termination impedance to the differential IO pins. The transistors can be turned ON or OFF separately to change the impedance termination.

    摘要翻译： 电路和方法用于集成电路上的阻抗终端。 在集成电路（IC）上形成电阻网络，为差分输入/输出（IO）引脚提供片内阻抗终端。 晶体管耦合在终端电阻网络中。 晶体管为差分IO引脚提供额外的终端阻抗。 晶体管可以单独打开或关闭，以改变阻抗终止。

    Schmitt trigger circuit with adjustable trip point voltages
    48.
    发明授权
    Schmitt trigger circuit with adjustable trip point voltages 有权
    施密特触发电路具有可调跳闸点电压

    公开(公告)号：US06870413B1

    公开(公告)日：2005-03-22

    申请号：US10017933

    申请日：2001-12-14

    申请人： Tzung-Chin Chang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Bonnie Wang ,  Yan Chong ,  Xiaobao Wang ,  Philip Pan ,  Gopinath Rangan ,  In Whan Kim

    发明人： Tzung-Chin Chang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Bonnie Wang ,  Yan Chong ,  Xiaobao Wang ,  Philip Pan ,  Gopinath Rangan ,  In Whan Kim

    IPC分类号： H03K3/3565 ,  H03K3/012

    CPC分类号： H03K3/3565

    摘要： A Schmitt trigger circuit has an adjustable hysteresis characteristic by providing a plurality of feedback circuits that differently affect at least one, and preferably both, of the circuit's upper trip point level and lower trip point level. The upper trip point level can be adjusted by selecting a desired feedback circuit from a first set of feedback circuits, and/or the lower trip point level can be adjusted by selecting a desired feedback circuit from a second set of feedback circuits. Feedback circuit selection is achieved by one or more control signals that may be programmable. The hysteresis characteristic can be adjusted to meet desired noise margin, delay, and input recognition criteria at different VCC levels. The Schmitt trigger circuit may be a CMOS Schmitt trigger with two input stage NMOS, two input stage PMOS transistors, a first set of NMOS feedback circuits, and a second set of PMOS feedback circuits.

    摘要翻译： 施密特触发电路具有可调滞后特性，通过提供多个反馈电路，其不同地影响电路的上跳点电平和较低跳变点电平的至少一个，优选两者。 可以通过从第一组反馈电路中选择所需的反馈电路来调整上跳点电平，和/或可以通过从第二组反馈电路中选择所需的反馈电路来调整下跳变点电平。 反馈电路选择由一个或多个可编程的控制信号来实现。 可以调节滞后特性，以满足不同VCC电平下的所需噪声容限，延迟和输入识别准则。 施密特触发电路可以是具有两个输入级NMOS，两个输入级PMOS晶体管，第一组NMOS反馈电路组和第二组PMOS反馈电路的CMOS施密特触发器。

    On-chip impedance matching circuit
    49.
    发明授权
    On-chip impedance matching circuit 有权
    片内阻抗匹配电路

    公开(公告)号：US06798237B1

    公开(公告)日：2004-09-28

    申请号：US10044365

    申请日：2002-01-11

    申请人： Xiaobao Wang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen

    发明人： Xiaobao Wang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen

    IPC分类号： H03K1716

    CPC分类号： H04L25/0278

    摘要： Integrated circuits with on-chip impedance matching techniques, which greatly reduce the number of off-chip resistors that are coupled to the integrated circuit, are provided. On-chip impedance matching circuits of the present invention are associated with each of a plurality of I/O pins on an integrated circuit. Circuitry of the present invention may include a resistor divider that has a resistor and an on-chip transistor. The resistance of the on-chip transistor and a voltage output signal of the resistor divider vary with process, temperature, and voltage of the integrated circuit. The effective channel W/L ratio of the impedance matching circuit changes in response to the voltage output signal of the resistor divider, so that changes in the impedance of the impedance matching circuit caused by the variations in process, temperature, and voltage are minimized.

    摘要翻译： 提供具有片上阻抗匹配技术的集成电路，其大大减少耦合到集成电路的片外电阻器的数量。 本发明的片上阻抗匹配电路与集成电路上的多个I / O引脚中的每一个相关联。 本发明的电路可以包括具有电阻器和片上晶体管的电阻分压器。 片上晶体管的电阻和电阻分压器的电压输出信号随集成电路的工艺，温度和电压而变化。 阻抗匹配电路的有效通道W / L比随着电阻分压器的电压输出信号而变化，使得由过程，温度和电压变化引起的阻抗匹配电路的阻抗变化最小化。