公开(公告)号：US07868673B2

公开(公告)日：2011-01-11

申请号：US12698606

申请日：2010-02-02

申请人： Hyun-Woo Lee ,  Won-Joo Yun ,  Dong-Suk Shin

发明人： Hyun-Woo Lee ,  Won-Joo Yun ,  Dong-Suk Shin

IPC分类号： H03L7/06

CPC分类号： G11C7/02 ,  G11C5/143 ,  G11C5/144 ,  G11C7/22 ,  G11C7/222

摘要： A power-down mode control apparatus includes an internal power-down control block configured to receive a locking completion signal and to generate an internal power-down signal, which is toggled for a predetermined time; a noise check block configured to check occurrence/non-occurrence of noise on the basis of a phase detection signal and to generate a plurality of power-down selection signals in response to the locking completion signal and the internal power-down signal; and a power-down enter control block configured to generate a plurality of power-down enter signals, which instruct individual circuits to enter a power-down mode in response to a reference clock signal, the plurality of power-down selection signals, a power-down mode signal, and the internal power-down signal.

摘要翻译： 断电模式控制装置包括内部掉电控制块，其被配置为接收锁定完成信号并产生切换预定时间的内部掉电信号; 噪声检查块，被配置为基于相位检测信号来检查噪声的发生/不发生，并且响应于锁定完成信号和内部掉电信号而产生多个掉电选择信号; 以及断电进入控制块，被配置为产生多个断电输入信号，其响应于参考时钟信号指示各个电路进入掉电模式，所述多个掉电选择信号，功率 下降模式信号和内部掉电信号。

公开(公告)号：US07755405B2

公开(公告)日：2010-07-13

申请号：US12172137

申请日：2008-07-11

申请人： Won-Joo Yun ,  Hyun-Woo Lee

发明人： Won-Joo Yun ,  Hyun-Woo Lee

IPC分类号： H03L7/06

CPC分类号： H03L7/07 ,  H03L7/0805 ,  H03L7/0814

摘要： A delay locked loop (DLL) circuit includes a first delay control unit configured to generate a first delay control signal in response to a first phase detection signal to control a delay amount of a first delay line and to output a first delay amount information signal, a second delay control unit configured to generate a second delay control signal in response to a second phase detection signal to control a delay amount of a second delay line and to output a second delay amount information signal, and to control the delay amount of the second delay line again in response to the first delay control signal and a half cycle information signal, a half cycle detecting unit configured to receive the first delay amount information signal and the second delay amount information signal to extract half cycle information of a reference clock signal, thereby generating the half cycle information signal, and a duty cycle correcting unit configured to combine an output clock signal from the first delay line and an output clock signal from the second delay line, thereby outputting a duty ratio correction clock signal.

摘要翻译： 延迟锁定环路（DLL）电路包括：第一延迟控制单元，被配置为响应于第一相位检测信号产生第一延迟控制信号，以控制第一延迟线的延迟量并输出第一延迟量信息信号， 第二延迟控制单元，被配置为响应于第二相位检测信号产生第二延迟控制信号，以控制第二延迟线的延迟量并输出第二延迟量信息信号，并且控制第二延迟控制信号的延迟量 延迟线响应于第一延迟控制信号和半周期信息信号，半周期检测单元被配置为接收第一延迟量信息信号和第二延迟量信息信号以提取参考时钟信号的半周期信息， 从而生成半周期信息信号，以及占空比校正单元，被配置为组合来自第一d的输出时钟信号 elay线和来自第二延迟线的输出时钟信号，从而输出占空比校正时钟信号。

公开(公告)号：US07683684B2

公开(公告)日：2010-03-23

申请号：US12175212

申请日：2008-07-17

申请人： Hyun-Woo Lee ,  Won-Joo Yun ,  Dong-Suk Shin

发明人： Hyun-Woo Lee ,  Won-Joo Yun ,  Dong-Suk Shin

IPC分类号： H03L7/06

CPC分类号： G11C7/02 ,  G11C5/143 ,  G11C5/144 ,  G11C7/22 ,  G11C7/222

摘要： A power-down mode control apparatus includes an internal power-down control block configured to receive a locking completion signal and to generate an internal power-down signal, which is toggled for a predetermined time; a noise check block configured to check occurrence/non-occurrence of noise on the basis of a phase detection signal and to generate a plurality of power-down selection signals in response to the locking completion signal and the internal power-down signal; and a power-down enter control block configured to generate a plurality of power-down enter signals, which instruct individual circuits to enter a power-down mode in response to a reference clock signal, the plurality of power-down selection signals, a power-down mode signal, and the internal power-down signal.

摘要翻译： 断电模式控制装置包括内部掉电控制块，其被配置为接收锁定完成信号并产生切换预定时间的内部掉电信号; 噪声检查块，被配置为基于相位检测信号来检查噪声的发生/不发生，并且响应于锁定完成信号和内部掉电信号而产生多个掉电选择信号; 以及断电进入控制块，被配置为产生多个断电输入信号，其响应于参考时钟信号指示各个电路进入掉电模式，所述多个掉电选择信号，功率 下降模式信号和内部掉电信号。

公开(公告)号：US20090316122A1

公开(公告)日：2009-12-24

申请号：US12486458

申请日：2009-06-17

申请人： Vitaliy Prosyentsov ,  Sanjaysingh Lalbahadoersing ,  Sami Musa ,  Hyun-Woo Lee

发明人： Vitaliy Prosyentsov ,  Sanjaysingh Lalbahadoersing ,  Sami Musa ,  Hyun-Woo Lee

IPC分类号： G03B27/52

CPC分类号： G03B27/52 ,  G03F7/70341 ,  G03F7/707 ,  G03F7/7085

摘要： A substrate stage for an immersion type lithographic apparatus is arranged to project a patterned radiation beam from a patterning device onto a substrate, the substrate stage being constructed to hold the substrate and including at least a sensor for sensing the patterned radiation beam, the sensor including an at least partially transmissive layer having a front side facing the incoming radiation beam and a back side opposite the front side, wherein the back side is provided with at least a sensor mark to be subjected to the radiation beam transmitted through the layer.

摘要翻译： 用于浸入式光刻设备的衬底台被布置成将来自图案形成装置的图案化辐射束投影到衬底上，衬底台被构造成保持衬底并且至少包括用于感测图案化辐射束的传感器，传感器包括 至少部分透射层，其具有面向所述入射辐射束的前侧和与所述前侧相对的后侧，其中，所述后侧设置有至少一个传感器标记，所述传感器标记经受穿过所述层的辐射束。

公开(公告)号：US07512086B2

公开(公告)日：2009-03-31

申请号：US09879651

申请日：2001-06-12

申请人： Sung-Ho Choi ,  Kook-Heui Lee ,  Hyun-Woo Lee ,  Seong-Ill Park ,  Sung-Oh Hwang ,  Jae-Yoel Kim ,  Byung-Jae Kwak

发明人： Sung-Ho Choi ,  Kook-Heui Lee ,  Hyun-Woo Lee ,  Seong-Ill Park ,  Sung-Oh Hwang ,  Jae-Yoel Kim ,  Byung-Jae Kwak

IPC分类号： H04Q7/20

CPC分类号： H04W74/008 ,  H04W52/50 ,  H04W56/00 ,  H04W74/0833

摘要： Disclosed is an uplink random access procedure in an NB-TDD (Narrow Band Time Division Duplexing) system. To achieve an acknowledgement for data transmission from a UTRAN (UMTS Terrestrial Radio Access Network), a UE selects one of a plurality of sync codes by which the UTRAN identifies UEs that request data transmission and transmits the selected sync code in a time slot of a sub-frame to the UTRAN. Then, the UE receives the sync code information, information about the arrival time of the sync code, time update information indicating a variation in the transmission time of data, and power information indicating an adjustment to a power gain in the UE from the UTRAN on an FPACH (Fast Physical Access Channel). The UE transmits the data on a P-RACH (Physical Random Access Channel) mapped from the FPACH according to the time update information and the power information.

摘要翻译： 公开了NB-TDD（窄带时分双工）系统中的上行链路随机接入过程。 为了实现对来自UTRAN（UMTS陆地无线电接入网络）的数据传输的确认，UE选择多个同步码中的一个，UTRAN通过该标识来识别请求数据传输的UE，并在所选择的同步码的时隙中发送所选择的同步码 子帧到UTRAN。 然后，UE接收同步码信息，关于同步码的到达时间的信息，指示数据的发送时间的变化的时间更新信息，以及表示UE中的来自UTRAN的功率增益的调整的功率信息， FPACH（快速物理访问频道）。 UE根据时间更新信息和功率信息，在从FPACH映射的P-RACH（物理随机接入信道）上发送数据。

公开(公告)号：US07381121B2

公开(公告)日：2008-06-03

申请号：US10580617

申请日：2005-02-16

申请人： Eu-Gene Song ,  Ju-Yeol Lee ,  Sung-Min Kim ,  Jae-Seok Kim ,  Hyun-Woo Lee

发明人： Eu-Gene Song ,  Ju-Yeol Lee ,  Sung-Min Kim ,  Jae-Seok Kim ,  Hyun-Woo Lee

IPC分类号： B24D11/00

CPC分类号： B24D11/02 ,  B24B37/22

摘要： Disclosed is a base pad of polishing pad, which is used in conjunction with polishing slurry during a chemical-mechanical polishing or planarizing process, and a multilayer pad using the same. Since the base pad according to the present invention does not have fine pores, it is possible to prevent permeation of polishing slurry and water and to avoid non uniformity of physical properties. Thereby, it is possible to lengthen the lifetime of the polishing pad.

摘要翻译： 公开了一种在化学机械抛光或平面化处理过程中与抛光浆料结合使用的抛光垫的基垫，以及使用其的多层垫。 由于根据本发明的基垫不具有细孔，因此可以防止研磨浆和水的渗透，并且可以避免物理性质的不均匀。 由此，可以延长抛光垫的寿命。

公开(公告)号：US20080088349A1

公开(公告)日：2008-04-17

申请号：US11987935

申请日：2007-12-06

申请人： Hyun-Woo Lee

发明人： Hyun-Woo Lee

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/095

摘要： A delay locked loop (DLL) device includes a first and a second input buffers for receiving an external clock, a multiplexer for selectively outputting a first and a second internal clocks based on a most significant bit (MSB) signal, a delay means for delaying the first and the second internal clock which is selected by the multiplexer, a phase detector for comparing a phase of the first internal clock with that of a feedback clock which is feedbacked from the delay means to thereby output a comparing signal, a low pass filter (LPF) mode generator for outputting a locking signal, which checks a locking state of the feedback clock based on the comparing signal and a first and a second control signals, to the delay means, and a low pass filter for receiving the comparing signal to inform whether or not the comparing signal is erroneous to the delay means.

摘要翻译： 延迟锁定环（DLL）装置包括用于接收外部时钟的第一和第二输入缓冲器，用于基于最高有效位（MSB）信号选择性地输出第一和第二内部时钟的多路复用器，用于延迟的延迟装置 由多路复用器选择的第一和第二内部时钟，相位检测器，用于将第一内部时钟的相位与从延迟装置反馈的反馈时钟的相位进行比较，从而输出比较信号;低通滤波器 （LPF）模式发生器，用于输出锁定信号，该锁定信号基于比较信号和第一和第二控制信号检测反馈时钟的锁定状态到延迟装置;以及低通滤波器，用于接收比较信号 通知比较信号是否对延迟装置是错误的。

公开(公告)号：US07282974B2

公开(公告)日：2007-10-16

申请号：US11323912

申请日：2005-12-29

申请人： Hyun-Woo Lee

发明人： Hyun-Woo Lee

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/0818 ,  H03L7/087

摘要： A DLL for reducing jitter during a high frequency operation by separately controlling a coarse delay and a fine delay. The DLL includes a multiplexing unit for selectively outputting one of the rising clock and the falling clock; a first delay line for generating a first internal clock and a second internal clock; a second delay line for generating a first clock and a second clock; a delay line control unit for controlling the second delay line; a phase control unit for generating a first DLL clock and a second DLL clock by mixing the first clock and the second clock; and a phase comparing unit for comparing the first DLL clock and the second DLL clock with the rising clock to generate a lock signal for controlling an operation timing of the first delay line and the second delay line.

摘要翻译： 用于通过分别控制粗略延迟和精细延迟来在高频操作期间减少抖动的DLL。 DLL包括用于选择性地输出上升时钟和下降时钟之一的复用单元; 用于产生第一内部时钟和第二内部时钟的第一延迟线; 用于产生第一时钟和第二时钟的第二延迟线; 延迟线控制单元，用于控制第二延迟线; 相位控制单元，用于通过混合第一时钟和第二时钟来产生第一DLL时钟和第二DLL时钟; 以及相位比较单元，用于将第一DLL时钟和第二DLL时钟与上升时钟进行比较，以产生用于控制第一延迟线和第二延迟线的操作定时的锁定信号。

公开(公告)号：US07165208B2

公开(公告)日：2007-01-16

申请号：US10852416

申请日：2004-05-24

申请人： Jae-Yoel Kim ,  Hyun-Woo Lee ,  Seong-Ill Park ,  Ho-Kyu Choi

发明人： Jae-Yoel Kim ,  Hyun-Woo Lee ,  Seong-Ill Park ,  Ho-Kyu Choi

IPC分类号： H03M3/00 ,  H03M3/03

CPC分类号： H04L1/0057 ,  H03M13/136 ,  H03M13/47 ,  H03M13/618 ,  H04B1/707 ,  H04L1/0025 ,  H04L1/0041 ,  H04L1/0069 ,  H04L1/0072 ,  H04L5/023

摘要： Disclosed is an apparatus for encoding k consecutive inputs indicating a TFCI (Transport Format Combination Indicator) of each of successively transmitted frames into a sequence of m symbols in an NB-TDD (Narrowband-Time Division Duplex) mobile communication system. An encoder encodes the k input bits into a sequence of at least 2n symbols where 2n>m, using an extended Reed-Muller code from a Kasami sequence. A puncturer performs puncturing on the sequence of 2n symbols from the encoder so as to output a sequence of m symbols.

摘要翻译： 公开了一种用于在NB-TDD（窄带 - 时分双工）移动通信系统中将连续发送的帧中的每一个的TFCI（传输格式组合指示符）编码为m个符号序列的k个连续输入的装置。 使用来自Kasami序列的扩展Reed-Muller码，编码器将k个输入比特编码为至少2个符号的序列，其中2 m。 穿刺器对来自编码器的2 符号的序列执行穿孔，以输出m个符号的序列。

公开(公告)号：US06956829B2

公开(公告)日：2005-10-18

申请号：US09989233

申请日：2001-11-19

申请人： Hyun-Woo Lee ,  Sung-Ho Choi ,  Kook-Heui Lee ,  Byung-Jae Kwak ,  Do-Young Kim ,  Sung-Oh Hwang

发明人： Hyun-Woo Lee ,  Sung-Ho Choi ,  Kook-Heui Lee ,  Byung-Jae Kwak ,  Do-Young Kim ,  Sung-Oh Hwang

IPC分类号： H04B17/00 ,  G01S13/74 ,  H04B7/26 ,  H04J3/00 ,  H04J13/00 ,  H04W24/08 ,  H04W52/04 ,  H04W64/00 ,  H04Q7/38

CPC分类号： H04W56/001 ,  H04B7/2618 ,  H04B7/2668 ,  H04B7/2681 ,  H04W56/0045 ,  H04W56/0065 ,  H04W92/10

摘要： Disclosed is a method for measuring a propagation delay value of a frame transmitted by a UE (User Equipment) to a Node B in a TDD (Time Division Duplexing) mobile communication system. The UE acquires synchronization with the Node B based on a downlink pilot channel signal transmitted in a period of a downlink pilot time slot, and determines an estimated round trip delay value T1 by comparing transmission power of a physical common channel signal in a first time slot with reception power of the same signal. The UE receives a transmission point correcting value T2 through a forward physical access channel (FPACH) signal transmitted from the Node B in a period of one downlink time slot among the time slots, and transmits a physical random access channel (PRACH) message with the estimated round trip delay value T1 at a transmission point determined based on T2 and T1.

摘要翻译： 公开了一种用于在TDD（时分双工）移动通信系统中测量UE（用户设备）向节点B发送的帧的传播延迟值的方法。 UE基于在下行链路导频时隙的周期中发送的下行链路导频信道获取与节点B的同步，并且通过在第一时间内比较物理公共信道信号的发送功率来确定估计的往返延迟值T 1 时隙具有相同信号的接收功率。 UE通过在时隙中的一个下行链路时隙的周期内从节点B发送的前向物理接入信道（FPACH）信号接收发送点校正值T 2，并且发送具有 在基于T 2和T 1确定的传输点处的估计往返延迟值T 1。