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公开(公告)号：US08282842B2
公开(公告)日：2012-10-09
申请号：US11946875
申请日：2007-11-29
申请人： Chieh-Ju Wang , Jyh-Cherng Yau , Yu-Tsung Lai , Jiunn-Hsiung Liao
发明人： Chieh-Ju Wang , Jyh-Cherng Yau , Yu-Tsung Lai , Jiunn-Hsiung Liao
IPC分类号： H01B13/00
CPC分类号： H01L21/02063 , H01L21/31144 , H01L21/76811 , H01L21/76813 , H01L21/76814
摘要： A cleaning method following an opening etching is provided. First, a semiconductor substrate having a dielectric layer is provided. The hard mask layer includes at least a metal layer. The opening etch is then carried out to form at least an opening in the dielectric layer. A nitrogen (N2) treatment process is performed to clean polymer residues having carbon-fluorine (C—F) bonds remained in the opening. Finally, a wet cleaning process is performed.
摘要翻译： 提供了开口蚀刻后的清洁方法。 首先，提供具有电介质层的半导体基板。 硬掩模层至少包括金属层。 然后进行开口蚀刻以形成电介质层中的至少一个开口。 进行氮（N2）处理工艺以清洁残留在开口中的具有碳 - 氟（C-F）键的聚合物残基。 最后，进行湿式清洗处理。
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公开(公告)号：US08277674B2
公开(公告)日：2012-10-02
申请号：US12637762
申请日：2009-12-15
申请人： Chang-Hsiao Lee , Yu-Tsung Lai , Jiunn-Hsiung Liao
发明人： Chang-Hsiao Lee , Yu-Tsung Lai , Jiunn-Hsiung Liao
IPC分类号： C23F1/00
CPC分类号： H01L21/31144 , H01L21/02071 , H01L21/32138
摘要： A method of removing post-etch residues is provided. First, a substrate is provided. An isolation layer covers the substrate and a conductive layer is embedded in the isolation layer. A dielectric layer and a hard mask cover the isolation layer. Then, an etching process is performed, and a patterned hard mask is formed by etching the hard mask by ions or atoms. After that, a charge-removing process is performed by using a conductive solution to cleaning the patterned hard mask and the dielectric layer so as to remove the charges accumulated on the patterned hard mask and the dielectric layer during the etch process. Finally, the post-etch residues on the patterned hard mask and the dielectric layer is removed.
摘要翻译： 提供了去除蚀刻后残留物的方法。 首先，提供基板。 隔离层覆盖基板，并且导电层嵌入在隔离层中。 介电层和硬掩模覆盖隔离层。 然后，进行蚀刻处理，通过用离子或原子蚀刻硬掩模来形成图案化的硬掩模。 之后，通过使用导电溶液来清洁图案化的硬掩模和电介质层，从而去除在刻蚀过程中累积在图案化的硬掩模和电介质层上的电荷，进行电荷去除处理。 最后，去除图案化硬掩模和电介质层上的蚀刻后残留物。
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公开(公告)号：US08252650B1
公开(公告)日：2012-08-28
申请号：US13092151
申请日：2011-04-22
申请人： Feng-Yi Chang , Yi-Po Lin , Jiunn-Hsiung Liao , Shang-Yuan Tsai , Chih-Wen Feng , Shui-Yen Lu , Ching-Pin Hsu
发明人： Feng-Yi Chang , Yi-Po Lin , Jiunn-Hsiung Liao , Shang-Yuan Tsai , Chih-Wen Feng , Shui-Yen Lu , Ching-Pin Hsu
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823864
摘要： A method for fabricating MOS transistor includes the steps of: overlapping a second stress layer on an etching stop layer and a first stress layer at a boundary region of the substrate; forming a dielectric layer on the first stress layer and the second stress layer; performing a first etching process to partially remove the dielectric layer for exposing a portion of the second stress layer at the boundary region; performing a second etching process to partially remove the exposed portion of the second stress layer for exposing the etching stop layer; performing a third etching process to partially remove the exposed portion of the etching stop layer for exposing the first stress layer at the boundary region; and performing a fourth etching process partially remove the exposed portion of the first stress layer.
摘要翻译： 一种用于制造MOS晶体管的方法包括以下步骤：在蚀刻停止层和基板的边界区域处的第一应力层上重叠第二应力层; 在所述第一应力层和所述第二应力层上形成介电层; 执行第一蚀刻工艺以部分去除所述电介质层以暴露所述边界区域处的所述第二应力层的一部分; 执行第二蚀刻工艺以部分地去除第二应力层的暴露部分以暴露蚀刻停止层; 执行第三蚀刻工艺以部分地去除用于在边界区域露出第一应力层的蚀刻停止层的暴露部分; 并且执行第四蚀刻工艺部分地去除第一应力层的暴露部分。
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公开(公告)号：US08137472B2
公开(公告)日：2012-03-20
申请号：US13161659
申请日：2011-06-16
申请人： Chang-Hsiao Lee , Shih-Fang Tzou , Ming-Da Hsieh , Yu-Tsung Lai , Jyh-Cherng Yau , Jiunn-Hsiung Liao
发明人： Chang-Hsiao Lee , Shih-Fang Tzou , Ming-Da Hsieh , Yu-Tsung Lai , Jyh-Cherng Yau , Jiunn-Hsiung Liao
IPC分类号： H01L21/302
CPC分类号： C11D11/0047 , C11D7/08 , C11D7/3281 , H01L21/02063 , H01L21/76811 , H01L21/76813 , H01L21/76814
摘要： A semiconductor process is provided. First, a metal layer, a dielectric layer and a patterned hard mask layer are sequentially formed on a substrate. Thereafter, a portion of the dielectric layer is removed to form an opening exposing the metal layer. Afterwards, a cleaning solution is used to clean the opening. The cleaning solution includes a triazole compound with a content of 0.00275 to 3 wt %, sulfuric acid with a content of 1 to 10 wt %, hydrofluoric acid with a content of 1 to 200 ppm and water. The semiconductor process can reduce the possibility of having an incomplete turning on, a leakage or a short, so that the yield of the product is increased.
摘要翻译： 提供半导体工艺。 首先，在基板上依次形成金属层，电介质层和图案化的硬掩模层。 此后，去除介电层的一部分以形成露出金属层的开口。 之后，使用清洁溶液清洁开口。 清洗液含有含量为0.00275〜3重量％的三唑化合物，含量为1〜10重量％的硫酸，含量为1〜200ppm的氢氟酸和水。 半导体工艺可以降低不完全打开，泄漏或短路的可能性，从而提高产品的产量。
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45.发明申请公开(公告)号：US20120061840A1
公开(公告)日：2012-03-15
申请号：US13298312
申请日：2011-11-17
IPC分类号： H01L23/532
CPC分类号： H01L21/76811
摘要： A dual damascene structure is disclosed. The dual damascene structure includes: a substrate comprising thereon a base dielectric layer and a lower wiring layer inlaid in the base dielectric layer; a dielectric layer on the substrate; a via opening in the dielectric layer, wherein the via opening misaligns with the lower wiring layer thus exposing a portion of the lower wiring layer and a portion of the base dielectric layer, wherein the via opening comprises a bottom including a recessed area; a barrier layer lining interior surface of the via opening and covers the exposed lower wiring layer and the base dielectric layer, wherein only the barrier layer fills the recessed area; and a copper layer filling the via opening on the barrier layer.
摘要翻译： 公开了一种双镶嵌结构。 双镶嵌结构包括：基底，其上包括镶嵌在基底介电层中的基底电介质层和下部布线层; 基底上的电介质层; 在所述电介质层中的通孔开口，其中所述通孔开口与所述下布线层不对准，从而暴露所述下布线层的一部分和所述基底电介质层的一部分，其中所述通孔开口包括具有凹陷区域的底部; 通过所述通孔开口的内表面的阻挡层，并且覆盖所述露出的下布线层和所述基底介电层，其中仅所述阻挡层填充所述凹陷区域; 以及填充阻挡层上的通孔开口的铜层。
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公开(公告)号：US08071487B2
公开(公告)日：2011-12-06
申请号：US11464496
申请日：2006-08-15
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/0271 , H01L21/0332 , H01L21/3081 , H01L21/32139
摘要： A stacked structure for patterning a material layer to form an opening pattern with a predetermined opening width in the layer is provided. The stacked structure includes an underlayer, a silicon rich organic layer, and a photoresist layer. The underlayer is on the material layer. The silicon rich organic layer is between the underlayer and the photoresist layer. The thickness of the photoresist layer is smaller than that of the underlayer and larger than two times of the thickness of the silicon rich organic layer. The thickness of the underlayer is smaller than three times of the predetermined opening width.
摘要翻译： 提供了用于图案化材料层以形成在该层中具有预定开口宽度的开口图案的层叠结构。 层叠结构包括底层，富硅有机层和光致抗蚀剂层。 底层在材料层上。 富硅有机层位于底层和光刻胶层之间。 光致抗蚀剂层的厚度小于底层的厚度，并且大于富硅有机层的厚度的两倍。 底层的厚度小于预定开口宽度的三倍。
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公开(公告)号：US20110254142A1
公开(公告)日：2011-10-20
申请号：US13167737
申请日：2011-06-24
IPC分类号： H01L29/02
CPC分类号： H01L21/0271 , H01L21/0332 , H01L21/3081 , H01L21/32139
摘要： A stacked structure for patterning a material layer to form an opening pattern with a predetermined opening width in the layer is provided. The stacked structure includes an underlayer, a silicon rich organic layer, and a photoresist layer. The underlayer is on the material layer. The silicon rich organic layer is between the underlayer and the photoresist layer. The thickness of the photoresist layer is smaller than that of the underlayer and larger than two times of the thickness of the silicon rich organic layer. The thickness of the underlayer is smaller than three times of the predetermined opening width.
摘要翻译： 提供了用于图案化材料层以形成在该层中具有预定开口宽度的开口图案的层叠结构。 层叠结构包括底层，富硅有机层和光致抗蚀剂层。 底层在材料层上。 富硅有机层位于底层和光刻胶层之间。 光致抗蚀剂层的厚度小于底层的厚度，并且大于富硅有机层的厚度的两倍。 底层的厚度小于预定开口宽度的三倍。
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公开(公告)号：US20110250751A1
公开(公告)日：2011-10-13
申请号：US12757017
申请日：2010-04-08
申请人： Chang-Hsiao Lee , Yu-Tsung Lai , Jiunn-Hsiung Liao
发明人： Chang-Hsiao Lee , Yu-Tsung Lai , Jiunn-Hsiung Liao
IPC分类号： H01L21/768
CPC分类号： H01L21/76804 , H01L21/02063 , H01L21/32139 , H01L21/76814
摘要： A method for filling a metal is disclosed. First, a substrate is provided. The substrate includes a metal material layer, a dielectric layer covering the metal material layer and a hard mask layer covering the dielectric layer. The hard mask layer has at least one opening to expose the underlying dielectric layer. Second, a dry etching step is performed to etch the dielectric layer through the opening to remove part of the dielectric layer to expose the metal material layer and to form a recess and leave some residues in the recess. Then a cleaning step is performed to remove the residues and to selectively remove part of the hard mask to substantially enlarge the opening. Later, a metal fills the recess through the enlarged opening.
摘要翻译： 公开了一种填充金属的方法。 首先，提供基板。 基板包括金属材料层，覆盖金属材料层的电介质层和覆盖电介质层的硬掩模层。 硬掩模层具有至少一个开口以暴露下面的介电层。 第二，进行干蚀刻步骤以通过开口蚀刻介电层以去除介电层的一部分以暴露金属材料层并形成凹槽并在凹部中留下一些残留物。 然后执行清洁步骤以去除残留物并选择性地去除硬掩模的一部分以基本上扩大开口。 之后，金属通过扩大的开口填充凹槽。
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公开(公告)号：US20110244678A1
公开(公告)日：2011-10-06
申请号：US13161659
申请日：2011-06-16
申请人： Chang-Hsiao LEE , Shih-Fang Tzou , Ming-Da Hsieh , Yu-Tsung Lai , Jyh-Cherng Yau , Jiunn-Hsiung Liao
发明人： Chang-Hsiao LEE , Shih-Fang Tzou , Ming-Da Hsieh , Yu-Tsung Lai , Jyh-Cherng Yau , Jiunn-Hsiung Liao
IPC分类号： H01L21/283
CPC分类号： C11D11/0047 , C11D7/08 , C11D7/3281 , H01L21/02063 , H01L21/76811 , H01L21/76813 , H01L21/76814
摘要： A semiconductor process is provided. First, a metal layer, a dielectric layer and a patterned hard mask layer are sequentially formed on a substrate. Thereafter, a portion of the dielectric layer is removed to form an opening exposing the metal layer. Afterwards, a cleaning solution is used to clean the opening. The cleaning solution includes a triazole compound with a content of 0.00275 to 3 wt %, sulfuric acid with a content of 1 to 10 wt %, hydrofluoric acid with a content of 1 to 200 ppm and water. The semiconductor process can reduce the possibility of having an incomplete turning on, a leakage or a short, so that the yield of the product is increased.
摘要翻译： 提供半导体工艺。 首先，在基板上依次形成金属层，电介质层和图案化的硬掩模层。 此后，去除介电层的一部分以形成露出金属层的开口。 之后，使用清洁溶液清洁开口。 清洗液含有含量为0.00275〜3重量％的三唑化合物，含量为1〜10重量％的硫酸，含量为1〜200ppm的氢氟酸和水。 半导体工艺可以降低不完全打开，泄漏或短路的可能性，从而提高产品的产量。
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公开(公告)号：US07977244B2
公开(公告)日：2011-07-12
申请号：US11611890
申请日：2006-12-18
IPC分类号： H01L21/302
CPC分类号： H01L21/31144 , H01L21/02063 , H01L21/31116 , H01L21/76811 , H01L21/76814 , Y10S438/906 , Y10S438/963
摘要： Disclosed is a semiconductor manufacturing process, in which a fluorine radical-containing plasma is used to etch a hard mask and a layer therebeneath; and a treatment is carried out using a gas reactive to fluorine radicals for reacting with residual fluorine radicals to form a fluorine-containing compound and remove it. Thus, precipitates formed by the reaction of fluorine radicals and titanium components existing in the hard mask to cause a process defect can be avoided.
摘要翻译： 公开了一种半导体制造方法，其中使用含氟自由基的等离子体来蚀刻硬掩模和其下面的层; 并且使用与氟自由基反应的气体与残留的氟自由基反应来进行处理以形成含氟化合物并除去。 因此，可以避免通过存在于硬掩模中的氟自由基和钛成分的反应形成的沉淀物引起工艺缺陷。
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