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    APPARATUS AND METHOD FOR DETECTING DISCONNECTION OF AN INTRAVASCULAR ACCESS DEVICE
    42.
    发明申请
    APPARATUS AND METHOD FOR DETECTING DISCONNECTION OF AN INTRAVASCULAR ACCESS DEVICE 审中-公开
    用于检测血管内通路装置断开的装置和方法

    公开(公告)号：US20110105877A1

    公开(公告)日：2011-05-05

    申请号：US12916021

    申请日：2010-10-29

    申请人： Michael J. Wilt ,  Jason M. Sachs ,  Kevin L. Grant

    发明人： Michael J. Wilt ,  Jason M. Sachs ,  Kevin L. Grant

    IPC分类号： A61B5/04

    CPC分类号： A61M1/3656 ,  A61M1/3653 ,  A61M1/3655 ,  A61M1/3659 ,  A61M2205/3317 ,  G01N27/07 ,  G01R27/14

    摘要： An apparatus and method are disclosed for detecting the disconnection of a vascular access device such as a needle, cannula or catheter from a blood vessel or vascular graft segment. A pair of electrodes is placed in direct contact with fluid or blood in fluid communication with the vascular segment. In one embodiment, the electrodes are incorporated into a pair of connectors connecting arterial and venous catheters to arterial and venous tubes leading to and from an extracorporeal blood flow apparatus. Wires leading from the electrodes to a detecting circuit can be incorporated into a pair of double lumen arterial and venous tubes connecting the blood flow apparatus to the blood vessel or vascular graft. The detecting circuit is configured to provide a low-voltage alternating current signal to the electrodes to measure the electrical resistance between the electrodes, minimizing both the duration and amount of current being delivered. Detection of an increase in electrical resistance between the electrodes exceeding a pre-determined threshold value may be used to indicate a possible disconnection of the vascular access device.

    摘要翻译： 公开了一种用于检测诸如针，插管或导管之类的血管进入装置与血管或血管移植物段断开的装置和方法。 一对电极被放置成与血管段流体连通的流体或血液直接接触。 在一个实施例中，电极被并入连接动脉和静脉导管到通向体外血液流动装置的动脉和静脉管的一对连接器。 从电极引导到检测电路的电线可以并入到将血流装置连接到血管或血管移植物的一对双腔动脉和静脉管中。 检测电路被配置为向电极提供低压交流信号以测量电极之间的电阻，从而最小化持续时间和传递的电流量。 检测超过预定阈值的电极之间的电阻增加可用于指示血管通路装置可能的断开。

    System and method for extracting image data
    45.
    发明授权
    System and method for extracting image data 失效
    用于提取图像数据的系统和方法

    公开(公告)号：US6041148A

    公开(公告)日：2000-03-21

    申请号：US25937

    申请日：1998-02-19

    申请人： Michael J. Wilt

    发明人： Michael J. Wilt

    IPC分类号： G06F13/40 ,  G06F15/00 ,  G06T1/20 ,  G06T1/60 ,  G06T3/40 ,  G06T5/20 ,  G06K9/56

    CPC分类号： G06T3/4007 ,  G06F13/4027 ,  G06T1/60 ,  G06T5/20

    摘要： A data extraction processor receives data, such as image data, at a high rate of speed and generates processed results, generally at a much lower overall data rate. This sort of processing is particularly useful for machine vision image data, because it can reduce a large image data set to a much smaller data set that is more immediately useful for the currently running application. The data extraction processor may include a segmentation processor, a gradient processor, or other similar types of data extraction processors. The disclosed data extraction processor includes a data flow controller which provides image data to the processors and receives the results from the processors. The data flow controller includes at least one FIFO (first-in, first-out) memory, which allows for the provision of data to the data extraction processor and the receipt of result data therefrom to occur at different rates. Since data extraction algorithms usually generate much less data that they receive, the data flow controller stalls the flow of output data while the analysis proceeds through the data. In some image-dependent situations, however, the analysis may generate more data than it receives. In these situations, the data flow controller stalls the incoming data while the additional results are generated.

    摘要翻译： 数据提取处理器以高速率接收诸如图像数据的数据，并且通常以低得多的总体数据速率产生处理结果。 这种处理对于机器视觉图像数据特别有用，因为它可以将大的图像数据集减少到对当前运行的应用更为直接有用的更小的数据集。 数据提取处理器可以包括分割处理器，梯度处理器或其他类似类型的数据提取处理器。 所公开的数据提取处理器包括数据流控制器，该数据流控制器向处理器提供图像数据并从处理器接收结果。 数据流控制器包括至少一个FIFO（先进先出）存储器，其允许向数据提取处理器提供数据并从其接收结果数据以不同的速率发生。 由于数据提取算法通常会生成少得多的数据，所以数据流控制器会在数据分析过程中阻止输出数据的流动。 然而，在某些图像相关的情况下，分析可能产生比它接收的更多的数据。 在这些情况下，数据流控制器会在输入附加结果生成时停止输入数据。

    Two-bit morphology processing apparatus and method
    47.
    发明授权
    Two-bit morphology processing apparatus and method 失效
    两位形态处理装置及方法

    公开(公告)号：US6038352A

    公开(公告)日：2000-03-14

    申请号：US26053

    申请日：1998-02-19

    申请人： Michael J. Wilt

    发明人： Michael J. Wilt

    IPC分类号： G06T1/60 ,  G06T5/20 ,  G06T5/30 ,  G06K9/56

    CPC分类号： G06T5/30 ,  G06T1/60

    摘要： The present invention provides a novel system and method that permits a "mask" to be directly incorporated into an image during image processing. This is accomplished by processing binary images or image data which are encoded using two bits rather than the usual one. The second bit is defined to be a "mask enable", which directs a processor to pass the original data through to the output image regardless of the processing result for that pixel. The present invention also provides a means of automatically providing background data to the processor for pixels outside the original image so that the result image is always the same size as the original image. For binary images, the background may be defined to have a value of "0" or "1", and this value is provided to the processing engine in place of all of the pixels which lie outside the original image. For gray-scale images, the minimum or maximum possible value is provided to the processing engine in place of all of the pixels which lie outside of the original image, effectively eliminating these values from consideration when the minimum or maximum of the neighborhood pixels is computed. The determination of whether a pixel is outside of the original image is implemented using the framing signals provided by a data flow controller along with the image data.

    摘要翻译： 本发明提供一种新颖的系统和方法，其允许在图像处理期间将“掩模”直接结合到图像中。 这是通过处理使用两个比特而不是常规编码的二进制图像或图像数据来实现的。 第二位被定义为“掩码使能”，其指示处理器将原始数据传递到输出图像，而不管该像素的处理结果如何。 本发明还提供了一种自动向处理器提供原始图像外的像素的背景数据的装置，使得结果图像总是与原始图像大小相同。 对于二进制图像，背景可以被定义为具有值“0”或“1”，并且该值被提供给处理引擎，而不是位于原始图像之外的所有像素。 对于灰度图像，将最小或最大可能值提供给处理引擎，代替位于原始图像之外的所有像素，当计算邻近像素的最小值或最大值时，有效地消除这些值。 。 使用由数据流控制器提供的成帧信号以及图像数据来确定像素是否在原始图像之外。

    Flexible processing hardware architecture
    48.
    发明授权
    Flexible processing hardware architecture 有权
    灵活的处理硬件架构

    公开(公告)号：US07062578B2

    公开(公告)日：2006-06-13

    申请号：US09977413

    申请日：2001-10-15

    申请人： David C. Davies ,  Michael P. Greenberg ,  Michael J. Wilt ,  John E. Agapakis

    发明人： David C. Davies ,  Michael P. Greenberg ,  Michael J. Wilt ,  John E. Agapakis

    IPC分类号： G06F13/00 ,  H04N7/14

    CPC分类号： G06F13/4027 ,  G06T1/60 ,  G06T5/20

    摘要： A flexible, reconfigurable processing system architecture allows for the implementation of a variety of processing system configurations to be implemented on a single device, which is preferably a PCI bus add-in extension board with an attached daughter card attached and electrically connected thereto through a PCI Mezzanine type connector, and which is plugged into a personal computer PCI expansion slot. The architecture uses the PCI bus, for example, as the local CPU bus for an embedded processor, which not only allows for flexibility in system configuration but also allows PCI devices to be hidden from the host CPU to allow for proper system startup. The architecture further permits an embedded processing CPU to be re-booted when the secondary PCI bus host bus bridge fails to respond without affecting host CPU or other secondary PCI bus peripheral devices. The architecture provides a method of loading an embedded system CPU's local memory with operating system and diagnostic code without the use of ROM or FLASH memory. A system and method of reserving memory is also disclosed which utilizes a dummy or surrogate board with little of no functionality but which has a class code of a common device such as an Ethernet card. The primary system BIOS will read the class code and reserve memory based on the surrogate card. The driver of the non-standard card such as an embedded processor, can then use the memory space allocated to the surrogate card by the BIOS.

    摘要翻译： 灵活的可重新配置的处理系统架构允许实现在单个设备上实施的各种处理系统配置，其优选地是PCI总线附加扩展板，附加的子卡通过PCI连接并与其电连接 夹层式连接器，并插入个人计算机PCI扩展槽。 该架构使用PCI总线作为嵌入式处理器的本地CPU总线，这不仅允许系统配置的灵活性，而且允许从主机CPU隐藏PCI设备以允许正确的系统启动。 当辅助PCI总线主机总线桥接器无法响应而不影响主机CPU或其他辅助PCI总线外围设备时，架构还允许重新引导嵌入式处理CPU。 该架构提供了一种使用操作系统和诊断代码加载嵌入式系统CPU本地存储器的方法，而无需使用ROM或FLASH存储器。 还公开了一种保留存储器的系统和方法，其利用具有很少功能但具有诸如以太网卡的公共设备的类代码的虚拟或替代板。 主系统BIOS将读取类代码，并根据代理卡预留内存。 非标准卡的驱动程序（如嵌入式处理器）可以使用由BIOS分配给替代卡的存储空间。

    Flexible processing hardware architecture
    49.
    发明授权
    Flexible processing hardware architecture 失效
    灵活的处理硬件架构

    公开(公告)号：US06308234B1

    公开(公告)日：2001-10-23

    申请号：US09030411

    申请日：1998-02-25

    申请人： David C. Davies ,  Michael P. Greenberg ,  Michael J. Wilt ,  John E. Agapakis

    发明人： David C. Davies ,  Michael P. Greenberg ,  Michael J. Wilt ,  John E. Agapakis

    IPC分类号： G06F1300

    CPC分类号： G06F13/4027 ,  G06T1/60 ,  G06T5/20

    摘要： A flexible, reconfigurable processing system architecture allows for the implementation of a variety of processing system configurations to be implemented on a single device, which is preferably a PCI bus add-in extension board with an attached daughter card attached and electrically connected thereto through a PCI Mezzanine type connector, and which is plugged into a personal computer PCI expansion slot. The architecture uses the PCI bus, for example, as the local CPU bus for an embedded processor, which not only allows for flexibility in system configuration but also allows PCI devices to be hidden from the host CPU to allow for proper system startup. The architecture further permits an embedded processing CPU to be re-booted when the secondary PCI bus host bus bridge fails to respond without affecting host CPU or other secondary PCI bus peripheral devices. The architecture provides a method of loading an embedded system CPU's local memory with operating system and diagnostic code without the use of ROM or FLASH memory. A system and method of reserving memory is also disclosed which utilizes a dummy or surrogate board with little of no functionality but which has a class code of a common device such as an Ethernet card. The primary system BIOS will read the class code and reserve memory based on the surrogate card. The driver of the non-standard card such as an embedded processor, can then use the memory space allocated to the surrogate card by the BIOS.

    摘要翻译： 灵活的可重新配置的处理系统架构允许实现在单个设备上实施的各种处理系统配置，其优选地是PCI总线附加扩展板，附加的子卡通过PCI连接并与其电连接 夹层式连接器，并插入个人计算机PCI扩展槽。 该架构使用PCI总线作为嵌入式处理器的本地CPU总线，这不仅允许系统配置的灵活性，而且允许从主机CPU隐藏PCI设备以允许正确的系统启动。 当辅助PCI总线主机总线桥接器无法响应而不影响主机CPU或其他辅助PCI总线外围设备时，架构还允许重新引导嵌入式处理CPU。 该架构提供了一种使用操作系统和诊断代码加载嵌入式系统CPU本地存储器的方法，而无需使用ROM或FLASH存储器。 还公开了一种保留存储器的系统和方法，其利用具有很少功能但具有诸如以太网卡的公共设备的类代码的虚拟或替代板。 主系统BIOS将读取类代码，并根据代理卡预留内存。 非标准卡的驱动程序（如嵌入式处理器）可以使用由BIOS分配给替代卡的存储空间。

    Morphology processing apparatus and method
    50.
    发明授权
    Morphology processing apparatus and method 有权
    形态处理装置及方法

    公开(公告)号：US06233369B1

    公开(公告)日：2001-05-15

    申请号：US09234396

    申请日：1999-01-20

    申请人： Michael J. Wilt

    发明人： Michael J. Wilt

    IPC分类号： G06K956

    CPC分类号： H04W4/00 ,  G06F13/4027 ,  G06T1/60 ,  G06T5/20 ,  H04L12/44

    摘要： The present invention provides a novel system and method that permits a “mask” to be directly incorporated into an image during image processing. This is accomplished by processing binary images or image data which are encoded using two bits rather than the usual one. The second bit is defined to be a “mask enable”, which directs a processor to pass the original data through to the output image regardless of the processing result for that pixel. The present invention also provides a means of automatically providing background data to the processor for pixels outside the original image so that the result image is always the same size as the original image. For binary images, the background may be defined to have a value of “0” or “1”, and this value is provided to the processing engine in place of all of the pixels which lie outside the original image. For gray-scale images, the minimum or maximum possible value is provided to the processing engine in place of all of the pixels which lie outside of the original image, effectively eliminating these values from consideration when the minimum or maximum of the neighborhood pixels is computed. The determination of whether a pixel is outside of the original image is implemented using the framing signals provided by a data flow controller along with the image data.

    摘要翻译： 本发明提供一种新颖的系统和方法，其允许在图像处理期间将“掩模”直接结合到图像中。 这是通过处理使用两个比特而不是常规编码的二进制图像或图像数据来实现的。 第二位被定义为“掩码使能”，其指示处理器将原始数据传递到输出图像，而不管该像素的处理结果如何。 本发明还提供了一种自动向处理器提供原始图像外的像素的背景数据的装置，使得结果图像总是与原始图像大小相同。 对于二进制图像，背景可以被定义为具有值“0”或“1”，并且该值被提供给处理引擎，而不是位于原始图像之外的所有像素。 对于灰度图像，将最小或最大可能值提供给处理引擎，代替位于原始图像之外的所有像素，当计算邻近像素的最小值或最大值时，有效地消除这些值。 。 使用由数据流控制器提供的成帧信号以及图像数据来确定像素是否在原始图像之外。