公开(公告)号：US08871595B2

公开(公告)日：2014-10-28

申请号：US13436878

申请日：2012-03-31

Applicant: Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sagy Levy

Inventor： Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sagy Levy

IPC: H01L21/8239

CPC classification number: H01L29/7833 ,  B82Y10/00 ,  H01L21/28282 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7836 ,  H01L29/7843 ,  H01L29/792 ,  H01L29/7926

Abstract: An embodiment of a method of integrating a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming in a first region of a substrate a channel of a memory device from a semiconducting material overlying a surface of the substrate, the channel connecting a source and a drain of the memory device; forming a charge trapping dielectric stack over the channel adjacent to a plurality of surfaces of the channel, wherein the charge trapping dielectric stack includes a blocking layer on a charge trapping layer over a tunneling layer; and forming a MOS device over a second region of the substrate.

Abstract translation: 描述了将非易失性存储器件集成到逻辑MOS流中的方法的实施例。 通常，该方法包括：在衬底的第一区域中形成存储器件的通道，覆盖衬底表面的半导体材料，连接存储器件的源极和漏极的沟道; 在与所述通道的多个表面相邻的所述通道上形成电荷捕获电介质堆叠，其中所述电荷捕获电介质堆叠包括在隧道层上的电荷捕获层上的阻挡层; 以及在所述衬底的第二区域上形成MOS器件。

公开(公告)号：US08643124B2

公开(公告)日：2014-02-04

申请号：US13007533

申请日：2011-01-14

Applicant: Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

Inventor： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

IPC: H01L21/336

CPC classification number: H01L29/512 ,  C23C16/0272 ,  C23C16/308 ,  G11C16/0466 ,  H01L21/0214 ,  H01L21/02271 ,  H01L21/28282 ,  H01L21/3145 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792

Abstract: A semiconductor device including a silicon-oxide-oxynitride-oxide-silicon structure and methods of forming the same are provided. Generally, the structure comprises: a tunnel oxide layer on a surface of a substrate including silicon; a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which the stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which the stoichiometric composition of the second oxynitride layer results in it being trap dense; a blocking oxide layer on the second oxynitride layer; and a silicon containing gate layer on the blocking oxide layer. Other embodiments are also disclosed.

Abstract translation: 提供了包括氧化硅 - 氧氮化物 - 氧化物 - 硅结构的半导体器件及其形成方法。 通常，该结构包括：在包括硅的衬底的表面上的隧道氧化物层; 多层电荷存储层，其包括在所述隧道氧化物层上的富氧第一氧氮化物层，其中所述第一氧氮化物层的化学计量组成导致其基本上不含杂质，并且所述第二氧氮化物层 第一氮氧化物层，其中第二氮氧化物层的化学计量组成导致其陷阱致密; 在第二氮氧化物层上的阻挡氧化物层; 以及在所述阻挡氧化物层上的含硅栅极层。 还公开了其他实施例。

公开(公告)号：US08592891B1

公开(公告)日：2013-11-26

申请号：US13539463

申请日：2012-07-01

Applicant: Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar ,  Jeong Byun

Inventor： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar ,  Jeong Byun

IPC: H01L29/76

CPC classification number: H01L29/4234 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor device and method of fabricating the same are provided. In one embodiment, the semiconductor device includes a memory transistor with an oxide-nitride-nitride-oxide (ONNO) stack disposed above a channel region. The ONNO stack comprises a tunnel dielectric layer disposed above the channel region, a multi-layer charge-trapping region disposed above the tunnel dielectric layer, and a blocking dielectric layer disposed above the multi-layer charge-trapping region. The multi-layer charge-trapping region includes a substantially trap-free layer comprising an oxygen-rich nitride and a trap-dense layer disposed above the trap-free layer. The semiconductor device further includes a strain inducing structure including a strain inducing layer disposed proximal to the ONNO stack to increase charge retention of the multi-layer charge-trapping region. Other embodiments are also disclosed.

Abstract translation: 提供了半导体器件及其制造方法。 在一个实施例中，半导体器件包括具有设置在沟道区上方的氧化氮化物 - 氮化物 - 氧化物（ONNO）堆的存储晶体管。 ONNO堆叠包括设置在沟道区上方的隧道介电层，设置在隧道介电层上方的多层电荷捕获区，以及设置在多层电荷俘获区上方的阻挡介质层。 多层电荷捕获区域包括基本上无陷阱层，其包含富含氧的氮化物和设置在无阱层之上的陷阱致密层。 半导体器件还包括应变诱导结构，其包括设置在ONNO堆叠附近的应变诱导层，以增加多层电荷俘获区域的电荷保留。 还公开了其他实施例。

公开(公告)号：US20130210209A1

公开(公告)日：2013-08-15

申请号：US13428201

申请日：2012-03-23

Applicant: Krishnaswamy Ramkumar

Inventor： Krishnaswamy Ramkumar

IPC: H01L21/336 ,  H01L21/28

CPC classification number: H01L27/11573 ,  H01L21/28282 ,  H01L21/823462 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/792

Abstract: Embodiments of a method of integration of a non-volatile memory device into a MOS flow are described. Generally, the method includes: forming a dielectric stack on a surface of a substrate, the dielectric stack including a tunneling dielectric overlying the surface of the substrate and a charge-trapping layer overlying the tunneling dielectric; forming a cap layer overlying the dielectric stack; patterning the cap layer and the dielectric stack to form a gate stack of a memory device in a first region of the substrate and to remove the cap layer and the charge-trapping layer from a second region of the substrate; and performing an oxidation process to form a gate oxide of a MOS device overlying the surface of the substrate in the second region while simultaneously oxidizing the cap layer to form a blocking oxide overlying the charge-trapping layer. Other embodiments are also disclosed.

Abstract translation: 描述了将非易失性存储器件集成到MOS流中的方法的实施例。 通常，所述方法包括：在衬底的表面上形成电介质叠层，所述电介质堆叠包括覆盖所述衬底表面的隧道电介质和覆盖所述隧道电介质的电荷捕获层; 形成覆盖在所述电介质叠层上的盖层; 图案化所述盖层和所述电介质堆叠以在所述衬底的第一区域中形成存储器件的栅极叠层，并且从所述衬底的第二区域去除所述覆盖层和所述电荷俘获层; 以及进行氧化处理，以形成覆盖在第二区域中的衬底的表面上的MOS器件的栅极氧化物，同时对盖层进行氧化以形成覆盖电荷俘获层的阻挡氧化物。 还公开了其他实施例。

公开(公告)号：US08080453B1

公开(公告)日：2011-12-20

申请号：US10186453

申请日：2002-06-28

Applicant: Alain Blosse ,  Krishnaswamy Ramkumar

Inventor： Alain Blosse ,  Krishnaswamy Ramkumar

IPC: H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/82345 ,  H01L21/823475 ,  H01L21/823871 ,  H01L29/78

Abstract: A semiconductor structure includes a semiconductor substrate, a gate layer containing silicon on the semiconductor substrate, a metallic layer on the gate layer, and a nitride layer on the metallic layer. The gate layer contains a P+ region and an N+ region.

Abstract translation: 半导体结构包括半导体衬底，在半导体衬底上含有硅的栅极层，栅极层上的金属层和金属层上的氮化物层。 栅极层包含P +区和N +区。

公开(公告)号：US20090032863A1

公开(公告)日：2009-02-05

申请号：US12005813

申请日：2007-12-27

Applicant: Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne

Inventor： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L21/3143 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518

Abstract: A method for forming a tunneling layer of a nonvolatile trapped-charge memory device and the article made thereby. The method includes multiple oxidation and nitridation operations to provide a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a tunneling layer having nitrogen at the substrate interface. The method provides for an improved memory window in a SONOS-type device. In one embodiment, the method includes an oxidation, a nitridation, a reoxidation and a renitridation. In one implementation, the first oxidation is performed with O2 and the reoxidation is performed with NO.

Abstract translation: 一种用于形成非易失性俘获电荷存储装置的隧道层的方法及其制成的制品。 该方法包括多次氧化和氮化操作，以提供比纯二氧化硅隧道层更高的介电常数，但是具有比在衬底界面处具有氮的隧穿层更少的氢和氮阱。 该方法提供了SONOS型设备中改进的存储器窗口。 在一个实施方案中，该方法包括氧化，氮化，再氧化和重新染色。 在一个实施方案中，首先用O 2进行氧化，并用NO进行再氧化。

公开(公告)号：US20080290399A1

公开(公告)日：2008-11-27

申请号：US11904475

申请日：2007-09-26

Applicant: Sagy Levy ,  Fredrick B. Jenne ,  Krishnaswamy Ramkumar

Inventor： Sagy Levy ,  Fredrick B. Jenne ,  Krishnaswamy Ramkumar

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/66833

Abstract: A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region and a pair of source/drain regions. A gate stack is above the substrate over the channel region and between the pair of source/drain regions. The gate stack includes a multi-layer charge-trapping region having a first deuterated layer. The multi-layer charge-trapping region may further include a deuterium-free charge-trapping layer.

Abstract translation: 描述了非易失性电荷陷阱存储器件。 该器件包括具有沟道区和一对源极/漏极区的衬底。 栅极堆叠在沟道区域上方之间以及在一对源极/漏极区域之间的衬底之上。 栅极堆叠包括具有第一氘化层的多层电荷捕获区域。 多层电荷俘获区域还可以包括不含氘的电荷俘获层。

公开(公告)号：US20080166893A1

公开(公告)日：2008-07-10

申请号：US11969125

申请日：2008-01-03

Applicant: Jeong Soo Byun ,  Krishnaswamy Ramkumar

Inventor： Jeong Soo Byun ,  Krishnaswamy Ramkumar

IPC: H01L21/321

CPC classification number: H01L21/28247 ,  H01L21/28044 ,  H01L29/4925

Abstract: A method of forming a semiconductor structure includes oxidizing a gate stack at a temperature of at most 600° C. with a plasma prepared from a gas mixture. The gas mixture includes an oxygen-containing gas and ammonia, and the gate stack is on a semiconductor substrate. The gate stack contains a gate layer, a conductive layer on the gate layer, a metal layer on the conductive layer, and a capping layer on the metal layer.

Abstract translation: 形成半导体结构的方法包括用气体混合物制备的等离子体在至多600℃的温度下氧化栅极叠层。 气体混合物包括含氧气体和氨，并且栅极堆叠在半导体衬底上。 栅极堆叠包含栅极层，栅极层上的导电层，导电层上的金属层和金属层上的覆盖层。

公开(公告)号：US07390750B1

公开(公告)日：2008-06-24

申请号：US11087924

申请日：2005-03-23

Applicant: Krishnaswamy Ramkumar ,  Alain P. Blosse ,  James A. Hunter

Inventor： Krishnaswamy Ramkumar ,  Alain P. Blosse ,  James A. Hunter

IPC: H01L21/302

CPC classification number: H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28132

Abstract: A method is provided which includes forming a hardmask feature adjacent to a patterned sacrificial structure of a semiconductor topography, selectively removing the patterned sacrificial structure to expose a lower layer and etching exposed portions of the lower layer in alignment with the hardmask feature. In some embodiments, forming the hardmask feature may include conformably depositing a hardmask material above the patterned sacrificial structure and lower layer as well as blanket etching the hardmask material such that upper surfaces of the patterned sacrificial structure and portions of the lower layer are exposed and portions of the hardmask material remain along sidewalls of the patterned sacrificial structure. The method may be applied to produce an exemplary semiconductor topography including a plurality of gate structures each having a width less than approximately 70 nm, wherein a variation of the widths among the plurality of gate structures is less than approximately 10%.

Abstract translation: 提供了一种方法，其包括形成与半导体形貌的图案化牺牲结构相邻的硬掩模特征，选择性地去除图案化的牺牲结构以暴露下层并蚀刻与硬掩模特征对准的下层的暴露部分。 在一些实施例中，形成硬掩模特征可以包括在图案化的牺牲结构和下层之上顺应地沉积硬掩模材料，以及橡皮布蚀刻硬掩模材料，使得图案化的牺牲结构的上表面和下层的部分被暴露， 硬掩模材料保留在图案化牺牲结构的侧壁上。 该方法可以应用于产生包括多个栅极结构的示例性半导体形貌，每个栅极结构的宽度小于约70nm，其中多个栅极结构之间的宽度变化小于约10％。

公开(公告)号：US07384833B2

公开(公告)日：2008-06-10

申请号：US11350160

申请日：2006-02-07

Applicant: Igor Polishchuk ,  Krishnaswamy Ramkumar ,  Sagy Charel Levy

Inventor： Igor Polishchuk ,  Krishnaswamy Ramkumar ,  Sagy Charel Levy

IPC: H01L21/336 ,  H01L21/8234

CPC classification number: H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

Abstract: In one embodiment, a self-aligned contact (SAC) trench structure is formed through a dielectric layer to expose an active region of a MOS transistor. The SAC trench structure not only exposes the active region for electrical connection but also removes portions of a stress liner over the active region. This leaves the stress liner mostly on the sidewall and top of the gate of the MOS transistor. Removing portions of the stress liner over the active region substantially removes the lateral component of the strain imparted by the stress liner on the substrate, allowing for improved drive current without substantially degrading a complementary MOS transistor.

Abstract translation: 在一个实施例中，通过电介质层形成自对准接触（SAC）沟槽结构以暴露MOS晶体管的有源区。 SAC沟槽结构不仅暴露用于电连接的有源区，而且还去除了有源区上的应力衬垫的部分。 这使得应力衬垫主要在MOS晶体管的侧壁和顶部上方。 在有源区上去除应力衬垫的部分基本上消除了由衬底上的应力衬垫施加的应变的横向分量，从而允许改进的驱动电流而不会使互补MOS晶体管基本上降级。