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    Data processing system with adjacent track interference metric
    45.
    发明授权
    Data processing system with adjacent track interference metric 有权
    具有相邻轨道干扰度量的数据处理系统

    公开(公告)号：US08861109B1

    公开(公告)日：2014-10-14

    申请号：US13963589

    申请日：2013-08-09

    Applicant: LSI Corporation

    Inventor： Eui Seok Hwang ,  Richard Rauschmayer ,  Shaohua Yang ,  Bruce Wilson

    IPC: G11B27/36

    CPC classification number: G11B5/02 ,  G11B20/10305 ,  G11B20/10472

    Abstract: A data processing circuit includes a long magnet identification circuit operable to identify long magnet bits in data to be processed, the long magnet bits comprising bits having a same value as a number of preceding and subsequent bits, an error calculation circuit operable to subtract an ideal version of the long magnet bits from the long magnet bits to yield an error signal, an adjacent track interference metric calculation circuit operable to calculate an adjacent track interference metric based on the error signal, and a comparator circuit operable to compare the adjacent track interference metric with a threshold value and to assert a refresh signal when the adjacent track interference metric is greater than the threshold value.

    Abstract translation: 数据处理电路包括：长磁体识别电路，用于识别要处理的数据中的长磁头位;所述长磁头位包括与前一位和后续位数相同值的位;误差计算电路，用于减去理想 版本的长磁头位产生误差信号，相邻轨道干扰度量计算电路，可操作以基于误差信号计算相邻轨道干扰度量;以及比较器电路，可操作以比较相邻轨道干扰度量 并且当相邻轨道干扰度量大于阈值时，断言刷新信号。

    Multi-level run-length limited finite state machine for magnetic recording channel
    46.
    发明授权
    Multi-level run-length limited finite state machine for magnetic recording channel 有权
    用于磁记录通道的多级游程限制有限状态机

    公开(公告)号：US08854755B2

    公开(公告)日：2014-10-07

    申请号：US13654893

    申请日：2012-10-18

    Applicant: LSI Corporation

    Inventor： Wu Chang ,  Razmik Karabed ,  Shaohua Yang ,  Fan Zhang

    IPC: G11B20/10 ,  G11B5/00 ,  G06F11/16 ,  G11B5/02

    CPC classification number: G11B5/02 ,  G06F11/16 ,  G11B20/10277

    Abstract: A system is described for constructing maximum transition run modulation code based upon a multi-level run-length limited finite state machine. A processor is configured to receive information from a hard disk drive via a read channel and recover data from the hard disk drive using maximum transition run modulation code. A memory has computer executable instructions configured for execution by the processor to model a magnetic recording channel as a partial response channel, model a source of information to the magnetic recording channel to provide an optimized Markov source, and construct a maximum transition run modulation code to mimic the optimized Markov source based upon a finite state machine having a limited transition run length and a multi-level periodic structure.

    Abstract translation: 描述了一种基于多级游程限制有限状态机来构建最大过渡运行调制码的系统。 处理器被配置为经由读取通道从硬盘驱动器接收信息，并使用最大过渡运行调制码从硬盘驱动器恢复数据。 存储器具有被配置为由处理器执行以将磁记录通道建模为部分响应通道的计算机可执行指令，将信息源建模到磁记录通道以提供优化马尔可夫源，并且构建最大过渡运行调制码 基于具有有限转换行程长度和多级周期性结构的有限状态机模拟优化的马尔可夫源。

    Majority-Tabular Post Processing of Quasi-Cyclic Low-Density Parity-Check Codes
    48.
    发明申请
    Majority-Tabular Post Processing of Quasi-Cyclic Low-Density Parity-Check Codes 有权
    准循环低密度奇偶校验码的大多数表格后处理

    公开(公告)号：US20140181624A1

    公开(公告)日：2014-06-26

    申请号：US13723357

    申请日：2012-12-21

    Applicant: LSI CORPORATION

    Inventor： Alexander S. Podkolzin ,  Shaohua Yang ,  Lav D. Ivanovic ,  Sergey Afonin

    IPC: H03M13/13

    CPC classification number: H03M13/1142

    Abstract: A method for finding a valid codeword based on a near codeword trapping in a low-density parity-check decoding process includes identifying trapping set configurations and applying corrections to produce trapping sets with a limited number of invalid checks. Trapping set configurations are corrected in order to produce a trapping set in a table of trapping sets, the table associating each corrected trapping set with a valid codeword.

    Abstract translation: 基于在低密度奇偶校验解码过程中捕获的近码字来找到有效码字的方法包括识别陷印集合配置和应用校正以产生具有有限数量的无效检查的陷印集合。 修正陷阱集合配置以便在陷阱集合表中产生陷阱集合，该表将每个校正的捕获集合与有效码字相关联。

    Low Density Parity Check Decoder With Miscorrection Handling
    50.
    发明申请
    Low Density Parity Check Decoder With Miscorrection Handling 有权
    低密度奇偶校验解码器与误码处理

    公开(公告)号：US20140164866A1

    公开(公告)日：2014-06-12

    申请号：US13708941

    申请日：2012-12-08

    Applicant: LSI CORPORATION

    Inventor： Anatoli A. Bolotov ,  Shaohua Yang ,  Zongwang Li ,  Mikhail I. Grinchuk ,  Lav D. Ivanovic ,  Fan Zhang ,  Yang Han

    IPC: H03M13/13

    CPC classification number: H03M13/13 ,  H03M13/1111 ,  H03M13/1142

    Abstract: A data processing system is disclosed including a decoder circuit, syndrome calculation circuit and hash calculation circuit. The decoder circuit is operable to apply a decoding algorithm to a decoder input based on a first portion of a composite matrix to yield a codeword. The syndrome calculation circuit is operable to calculate a syndrome based on the codeword and on the first portion of the composite matrix. The hash calculation circuit is operable to calculate a hash based on a second portion of the composite matrix. The decoder circuit is also operable to correct the codeword on the hash when the syndrome indicates that the codeword based on the first portion of the composite matrix is correct but a second test indicates that the codeword is miscorrected.

    Abstract translation: 公开了一种数据处理系统，包括解码器电路，校正子计算电路和散列计算电路。 解码器电路可操作以基于复合矩阵的第一部分将解码算法应用于解码器输入以产生码字。 校正子计算电路可操作以基于码字和复合矩阵的第一部分来计算校正子。 散列计算电路可操作以基于复合矩阵的第二部分来计算散列。 当校验子指示基于复合矩阵的第一部分的码字是正确的但是第二测试指示码字被修正时，解码器电路还可操作以校正散列上的码字。

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