公开(公告)号：US20220199639A1

公开(公告)日：2022-06-23

申请号：US17125407

申请日：2020-12-17

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Guan-Ru Lee

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11573

Abstract: The present disclosure provides a three-dimensional memory device and a method for manufacturing the same. The three-dimensional memory device includes a plurality of tiles, and each tiles includes a plurality of blocks, and each blocks includes a gate stacked structure, a conductive layer, first ring-shaped channel pillars, source/drain pillars, and charge storage structures. The gate stacked structure is disposed on the substrate and includes gate layers electrically insulated from each other. The conductive layer is disposed between the substrate and the gate stacked structure. The first ring-shaped channel pillars are disposed on the substrate and located in the gate stacked structure. The source/drain pillars are disposed on the substrate, and each of the first ring-shaped channel pillars are configured with two source/drain pillars disposed therein. Each of the charge storage structures is disposed between the corresponding gate layer and the corresponding first ring-shaped channel pillar. The conductive layer in one of the tiles is isolated from the conductive layers in the other tiles.

公开(公告)号：US11106396B1

公开(公告)日：2021-08-31

申请号：US16886251

申请日：2020-05-28

Applicant: MACRONIX International Co., Ltd.

Inventor： Po-Kai Hsu ,  Teng-Hao Yeh ,  Ming-Liang Wei ,  Hang-Ting Lue

IPC: G11C11/34 ,  G06F3/06 ,  G11C16/26 ,  G11C16/04

Abstract: A memory apparatus and compensation method for a computation result thereof are provided. The memory apparatus includes a memory sub-block, a reference memory sub-block and a control circuit. During a computation phase, the memory sub-block receives an input signal, and generates a computation result by a multiply-accumulate operation according to the input signal. The reference memory sub-block includes a plurality of memory cells pre-programmed with a reference weight value. The reference memory sub-block receives a reference input signal during a calibration phase, and generates a reference computation value by a multiply-accumulate operation according to the reference input signal and the reference weight value. The control circuit generates an adjustment value according to the reference computation value and a standard computation value, and during the computation phase, adjusts the computation result according to the adjustment value to generate an adjusted computation result.

公开(公告)号：US11081595B1

公开(公告)日：2021-08-03

申请号：US16877518

申请日：2020-05-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Cheng-Lin Sung ,  Pei-Ying Du ,  Hang-Ting Lue

IPC: G11C16/04 ,  H01L29/788 ,  G11C11/56 ,  H01L29/792

Abstract: A multi-gate transistor includes: a doped drain region; a doped source region; a gate group including a first gate and a second gate; a channel, the doped drain region and the doped source region being on respective two sides of the channel; and an interlayer, formed between the channel and the gate group, wherein a first gate voltage and a second gate voltage are applied to the first gate and the second gate of the gate group, respectively, the channel is induced as at least a P sub-channel and at least an N sub-channel and the multi-gate transistor equivalently behaves as a PNPN structure.

公开(公告)号：US20210158857A1

公开(公告)日：2021-05-27

申请号：US17077795

申请日：2020-10-22

Applicant: MACRONIX International Co., Ltd.

Inventor： Ming-Liang Wei ,  Po-Kai Hsu ,  Hang-Ting Lue ,  Teng-Hao Yeh

IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/4076 ,  G06F9/38

Abstract: An in-memory computing device including a plurality of memory cell arrays and a plurality of sensing amplifiers are provided. The memory cell arrays respectively receive a plurality of input signals. The input signals are divided into a plurality of groups. The groups respectively have at least one partial input signal. The at least one partial input signal of each of the groups has a same value. Numbers of the at least one partial input signal in the groups sequentially form a geometric sequence with a common ration equal to 2. The memory cell arrays respectively provide a plurality of weightings, and perform multiply-add operations respectively according to the received input signals and the weightings to generate a plurality of computation results. The sensing amplifiers respectively generate a plurality of sensing results according to the computation results.

公开(公告)号：US10916308B2

公开(公告)日：2021-02-09

申请号：US16784154

申请日：2020-02-06

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue

IPC: G11C16/14 ,  G11C16/04 ,  G11C5/02

Abstract: A three-dimensional (3D) flash memory module, a healing method of 3D flash memory, and an operating method of 3D flash memory are provided. The 3D flash memory module includes a 3D flash memory structure and a conductive layer. The 3D flash memory structure is disposed on a substrate. The conductive layer is disposed on the substrate and is adjacent to at least one side wall of the 3D flash memory structure. The conductive layer extends along the at least one side wall of the 3D flash memory structure, and each of two opposite end portions of the conductive layer has an electrical connection point in an extending direction of the conductive layer.

公开(公告)号：US10664746B2

公开(公告)日：2020-05-26

申请号：US16172921

申请日：2018-10-29

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue

IPC: G11C5/06 ,  G06N3/063 ,  H01L27/11578 ,  G06F7/544 ,  H01L27/02

Abstract: A neural network system for execution of a sum-of-products operation includes a memory device and a controller. The memory device includes a 3D array having a plurality of memory cells with programmable conductances disposed in cross-points of a plurality of cell body lines and gate lines, a gate driver coupled to the gate lines and applying control gate voltages in combination with the programmable conductances for corresponding to weights of terms in the sum-of-products operation, a input driver used to apply voltages to the memory cells corresponding to input variables, a plurality of input lines connecting the cell body lines to the input driver, a sensing circuit used to sense currents passing through the memory cells corresponding the terms in the sum-of-products operation, a buffer circuit used to store the terms. The controller is used to control the memory device summing up the terms in the sum-of-products operation.

公开(公告)号：US20190371804A1

公开(公告)日：2019-12-05

申请号：US15996617

申请日：2018-06-04

Applicant: Macronix International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Chih-Wei Hu ,  Hang-Ting Lue

IPC: H01L27/11556 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

Abstract: A memory device that includes: a memory controller; a control unit; and a memory cell array that includes memory blocks, each memory block comprising: memory cells, word lines respectively coupled to the memory cells, signal lines to transfer signals to perform programming operations to one or more memory cells of the memory cells, a first metal layer coupled to a first group of lines and configured to route the first group of the lines to the control unit, the lines comprising the word lines and the signal lines, and a second metal layer coupled to a second group of the lines and configured to route the second group of the lines to the control unit, wherein the memory controller is configured to: control the control unit to (i) select particular memory cells and (ii) program data to the particular memory cells is disclosed.

公开(公告)号：US20190156901A1

公开(公告)日：2019-05-23

申请号：US15818208

申请日：2017-11-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen Chen ,  Hang-Ting Lue

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/12 ,  G11C16/24

Abstract: A memory device includes a plurality of memory cells arranged in series in a semiconductor body. First and second dummy memory cells arranged in series between a first string select switch and a first edge memory cell at a first end of the plurality of memory cells. The first dummy memory cell is adjacent the first edge memory cell, and the second dummy memory cell is adjacent the first string select switch. A channel line includes channels for the plurality of memory cells and the first and second dummy memory cells. Control circuitry is adapted for programming a selected memory cell in the plurality of memory cells corresponding to a selected word line by applying a switching voltage to the first dummy memory cell, the switching voltage having a first voltage level during a first time interval, and thereafter changing to a second voltage level higher than the first voltage level.

公开(公告)号：US10141328B2

公开(公告)日：2018-11-27

申请号：US15379527

申请日：2016-12-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue ,  Wei-Chen Chen

IPC: H01L27/11582 ,  H01L21/02

Abstract: A 3D memory device includes a substrate, a ridge-shaped stack, a memory layer, a channel layer and a capping layer. The ridge-shaped stack includes a plurality of conductive strips extending along a first direction and stacked on the substrate. The memory layer is stacked on a vertical sidewall of the ridge-shaped stack along a second direction that forms a non-straight with the first direction. The channel layer is stacked on the memory layer along the second direction and has a narrow sidewall having a long side extending along the first direction. The capping layer is stacked on the narrow sidewall along a third direction that forms a non-straight angle with the second direction.

公开(公告)号：US09761319B1

公开(公告)日：2017-09-12

申请号：US15344614

申请日：2016-11-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuo-Pin Chang ,  Teng-Hao Yeh ,  Hang-Ting Lue

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/14

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445

Abstract: A reading method for preventing a read disturbance and a memory using the same are provided. The reading method includes the following steps: At least one of a plurality of string select lines is selected and a predetermined string select voltage is applied to the selected string select line. Only one of a plurality of ground select lines is selected and a predetermined ground select voltage is applied to the selected ground select line.