Device and method for improving reading speed of memory

    公开(公告)号:US09412425B2

    公开(公告)日:2016-08-09

    申请号:US14673530

    申请日:2015-03-30

    Abstract: A memory device includes a plurality of sense amplifiers coupled with an array of memory cells, a plurality of output data lines receiving outputs of corresponding sense amplifiers, and a plurality of precharge circuits configured to apply a precharge voltage on the output data lines. A controller provides control signals to the sense amplifiers and to the precharge circuits, including to cause the precharge circuits to precharge the output data lines before the sense amplifiers drive output data signals to the output data lines. The plurality of sense amplifiers includes banks of sense amplifiers, and each bank includes a sense amplifier having an output driving each output data line. The memory device includes data output multiplexers having inputs coupled to the output data lines, and the precharge circuits are coupled to the output data lines between outputs of the sense amplifiers and the data output multiplexers.

    Programming method, reading method and operating system for memory
    43.
    发明授权
    Programming method, reading method and operating system for memory 有权
    存储器的编程方法,读取方法和操作系统

    公开(公告)号:US09286158B2

    公开(公告)日:2016-03-15

    申请号:US14173873

    申请日:2014-02-06

    CPC classification number: G06F11/1072 G06F11/1012 H03M13/1575 H03M13/19

    Abstract: A programming method, a reading method and an operating system for a memory are provided. The programming method includes the following steps. A data is provided. A parity generation is performed to obtain an error-correcting code (ECC). The memory is programmed to record the data and the error-correcting code. The data is transformed before performing the parity generation, such that a hamming distance between two codes corresponding to two adjacent threshold voltage states in the data to be performed the parity generation is 1.

    Abstract translation: 提供了一种用于存储器的编程方法,读取方法和操作系统。 编程方法包括以下步骤。 提供数据。 执行奇偶校验生成以获得纠错码(ECC)。 存储器被编程为记录数据和纠错码。 在执行奇偶校验生成之前变换数据,使得对应于待执行奇偶产生的数据中的两个相邻阈值电压状态的两个代码之间的汉明距离为1。

    DEVICE AND METHOD FOR IMPROVING READING SPEED OF MEMORY
    44.
    发明申请
    DEVICE AND METHOD FOR IMPROVING READING SPEED OF MEMORY 审中-公开
    改进记忆速度的装置和方法

    公开(公告)号:US20150206557A1

    公开(公告)日:2015-07-23

    申请号:US14673530

    申请日:2015-03-30

    Abstract: A memory device includes a plurality of sense amplifiers coupled with an array of memory cells, a plurality of output data lines receiving outputs of corresponding sense amplifiers, and a plurality of precharge circuits configured to apply a precharge voltage on the output data lines. A controller provides control signals to the sense amplifiers and to the precharge circuits, including to cause the precharge circuits to precharge the output data lines before the sense amplifiers drive output data signals to the output data lines. The plurality of sense amplifiers includes banks of sense amplifiers, and each bank includes a sense amplifier having an output driving each output data line. The memory device includes data output multiplexers having inputs coupled to the output data lines, and the precharge circuits are coupled to the output data lines between outputs of the sense amplifiers and the data output multiplexers.

    Abstract translation: 存储器件包括与存储器单元阵列耦合的多个读出放大器,接收对应的读出放大器的输出的多个输出数据线以及被配置为在输出数据线上施加预充电电压的多个预充电电路。 控制器向读出放大器和预充电电路提供控制信号,包括在读出放大器将输出数据信号驱动到输出数据线之前使预充电电路对输出数据线进行预充电。 多个读出放大器包括读出放大器组,并且每个存储体包括具有驱动每个输出数据线的输出的读出放大器。 存储器件包括具有耦合到输出数据线的输入的数据输出多路复用器,并且预充电电路耦合到读出放大器和数据输出多路复用器的输出之间的输出数据线。

    Device and method for improving reading speed of memory
    45.
    发明授权
    Device and method for improving reading speed of memory 有权
    提高记忆体读取速度的装置和方法

    公开(公告)号:US09001604B2

    公开(公告)日:2015-04-07

    申请号:US13801500

    申请日:2013-03-13

    Abstract: A memory device includes a plurality of sense amplifiers coupled with an array of memory cells, a plurality of output data lines receiving outputs of corresponding sense amplifiers, and a plurality of precharge circuits configured to apply a precharge voltage on the output data lines. A controller provides control signals to the sense amplifiers and to the precharge circuits, including to cause the precharge circuits to precharge the output data lines before the sense amplifiers drive output data signals to the output data lines. The plurality of sense amplifiers includes banks of sense amplifiers, and each bank includes a sense amplifier having an output driving each output data line. The memory device includes data output multiplexers having inputs coupled to the output data lines, and the precharge circuits are coupled to the output data lines between outputs of the sense amplifiers and the data output multiplexers.

    Abstract translation: 存储器件包括与存储器单元阵列耦合的多个读出放大器,接收对应的读出放大器的输出的多个输出数据线以及被配置为在输出数据线上施加预充电电压的多个预充电电路。 控制器向读出放大器和预充电电路提供控制信号,包括在读出放大器将输出数据信号驱动到输出数据线之前使预充电电路对输出数据线进行预充电。 多个读出放大器包括读出放大器组,并且每个存储体包括具有驱动每个输出数据线的输出的读出放大器。 存储器件包括具有耦合到输出数据线的输入的数据输出多路复用器,并且预充电电路耦合到读出放大器和数据输出多路复用器的输出之间的输出数据线。

    Device and Method for Improving Reading Speed of Memory
    46.
    发明申请
    Device and Method for Improving Reading Speed of Memory 有权
    提高存储器读取速度的装置和方法

    公开(公告)号:US20140269125A1

    公开(公告)日:2014-09-18

    申请号:US13801500

    申请日:2013-03-13

    Abstract: A memory device includes a plurality of sense amplifiers coupled with an array of memory cells, a plurality of output data lines receiving outputs of corresponding sense amplifiers, and a plurality of precharge circuits configured to apply a precharge voltage on the output data lines. A controller provides control signals to the sense amplifiers and to the precharge circuits, including to cause the precharge circuits to precharge the output data lines before the sense amplifiers drive output data signals to the output data lines. The plurality of sense amplifiers includes banks of sense amplifiers, and each bank includes a sense amplifier having an output driving each output data line. The memory device includes data output multiplexers having inputs coupled to the output data lines, and the precharge circuits are coupled to the output data lines between outputs of the sense amplifiers and the data output multiplexers.

    Abstract translation: 存储器件包括与存储器单元阵列耦合的多个读出放大器,接收对应的读出放大器的输出的多个输出数据线以及被配置为在输出数据线上施加预充电电压的多个预充电电路。 控制器向读出放大器和预充电电路提供控制信号,包括在读出放大器将输出数据信号驱动到输出数据线之前使预充电电路对输出数据线进行预充电。 多个读出放大器包括读出放大器组,并且每个存储体包括具有驱动每个输出数据线的输出的读出放大器。 存储器件包括具有耦合到输出数据线的输入的数据输出多路复用器,并且预充电电路耦合到读出放大器和数据输出多路复用器的输出之间的输出数据线。

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