公开(公告)号：US20240096408A1

公开(公告)日：2024-03-21

申请号：US18371308

申请日：2023-09-21

Applicant: Micron Technology, Inc.

Inventor： Ching-Huang Lu ,  Yingda Dong

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4094

CPC classification number: G11C11/4096 ,  G11C11/4085 ,  G11C11/4094 ,  G11C2207/2254

Abstract: Control logic in a memory device receives a request to perform a read operation to read data from a memory array of a memory device, the request comprising an indication of a segment of the memory array where the data is stored, and performs a first coarse valley tracking calibration operation on the segment of the memory array. The control logic further configures a read voltage level and one or more parameters associated with the read operation based on a result of the first coarse valley tracking calibration operation and performs a second fine valley tracking calibration operation on the segment of the memory array using the configured read voltage level and the configured one or more parameters.

公开(公告)号：US20240061583A1

公开(公告)日：2024-02-22

申请号：US17889836

申请日：2022-08-17

Applicant: Micron Technology, Inc.

Inventor： Zhenming Zhou ,  Ching-Huang Lu ,  Murong Lang

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0679 ,  G06F3/0629

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a memory access operation on a set of cells associated with a wordline of the memory device; determining that the wordline is disposed on a first deck of the memory deck; responsive to determining that the wordline is disposed on the first deck, determining that the wordline is associated with a first group of wordlines associated with the first deck; and responsive to determining that the wordline is associated with the first group of wordlines associated with the first deck, performing the memory access operation on the set of cells connected to the wordline using a first time sense parameter, wherein the first time sense parameter corresponds to the first group of wordlines associated with the first deck.

公开(公告)号：US20240028253A1

公开(公告)日：2024-01-25

申请号：US18224538

申请日：2023-07-20

Applicant: Micron Technology, Inc.

Inventor： Avinash Rajagiri ,  Ching-Huang Lu ,  Aman Gupta ,  Shuji Tanaka ,  Masashi Yoshida ,  Shinji Sato ,  Yingda Dong

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory device can include a memory array coupled with a control logic. The control logic initiates a program operation on the memory array, the program operation including a program phase and a program recovery phase. The control logic causes a program voltage to be applied to a selected word line during the program phase. The control logic causes a select gate drain coupled with a string of memory cells to deactivate during the program recovery phase after applying the program voltage, where the string of memory cells include a plurality of memory cells each coupled to a corresponding word line of a plurality of wordlines. The control logic causes a voltage to be applied to a select gate source coupled with the string of memory cells to activate the select gate source during the program recovery phase concurrent to causing the select gate drain to deactivate.

公开(公告)号：US20230402103A1

公开(公告)日：2023-12-14

申请号：US17887765

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Jiun-horng Lai ,  Pitamber Shukla ,  Ching-Huang Lu ,  Chengkuan Yin ,  Yoshiaki Fukuzumi

IPC: G11C16/16 ,  G11C16/26 ,  G11C16/32

CPC classification number: G11C16/16 ,  G11C16/26 ,  G11C16/32

Abstract: A memory device includes a memory array comprising memory cells and control logic. The control logic performs operations including: causing a first erase pulse to be applied to a memory line of the memory array to perform an erase operation, the memory line being a conductive line coupled to a string of the memory cells; suspending the erase operation in response to receipt of a suspend command during a ramping period of the first erase pulse; recording a suspend voltage level of the first erase pulse when suspended; causing the erase operation to be resumed in response to an erase resume command; selectively modifying a pulse width of a flattop period of a second erase pulse based on the suspend voltage level; and causing the second erase pulse to be applied to the memory line during a resume of the erase operation.

公开(公告)号：US20230360708A1

公开(公告)日：2023-11-09

申请号：US17739789

申请日：2022-05-09

Applicant: Micron Technology, Inc.

Inventor： Pitamber Shukla ,  Jiun-Horng Lai ,  Ching-Huang Lu ,  Fulvio Rori ,  Wai Ying Lo ,  Scott A. Stoller

IPC: G11C16/16 ,  G11C16/34

CPC classification number: G11C16/16 ,  G11C16/3445

Abstract: Memory systems with flexible erase suspend-resume operations are described herein. In one embodiment, a memory device is configured to receive an erase suspend command while a first erase pulse of an erase operation is at a flattop voltage. In response, the memory device suspends the erase operation. The memory device further resumes the erase operation such that a second erase pulse of the erase operation is ramped to the flattop voltage. Absent intervening erase suspend operations, erase operations of the memory device can include a single erase pulse that remains at the flattop voltage for a total duration. A first total duration plus a second total duration the first and second erase pulses, respectively, remain at the flattop voltage remains less than or equal to the total duration the single erase pulse remains at the flattop voltage.

公开(公告)号：US20230360696A1

公开(公告)日：2023-11-09

申请号：US18142112

申请日：2023-05-02

Applicant: Micron Technology, Inc.

Inventor： Huai-Yuan Tseng ,  Akira Goda ,  Ching-Huang Lu ,  Eric N. Lee ,  Tomoharu Tanaka

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4093

CPC classification number: G11C11/4096 ,  G11C11/4085 ,  G11C11/4093

Abstract: A read is initiated with respect to a target cell. A pair of adjacent cells includes a first cell and a second cell each adjacent to the target cell. First cell state information is obtained for the first cell and second cell state information is obtained for the second cell. A state information bin is determined by applying a pre-defined operation to the first cell state information and the second cell state information of the respective pair of adjacent cells. The target cell is assigned to the state information bin. Each state information bin defines a read level offset for reading the target cell.

公开(公告)号：US20230195328A1

公开(公告)日：2023-06-22

申请号：US18082803

申请日：2022-12-16

Applicant: Micron Technology, Inc.

Inventor： Ching-Huang Lu ,  Yingda Dong ,  Sampath K. Ratnam

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0679 ,  G06F3/0652

Abstract: Control logic in a memory device executes a programming operation to program a memory cell of a set of memory cells to a programming level. A first erase sub-operation is executed to erase the memory cell to a first threshold voltage level, the first erase sub-operation including applying, to the memory cell, a first erase pulse having a first erase voltage level. A second erase sub-operation is executed to erase the memory cell to a second threshold voltage level, the second erase sub-operation including applying, to the memory cell, a second erase pulse having a second erase voltage level, where the first erase voltage level of the first erase pulse is lower than the second erase voltage level of the second erase pulse.

公开(公告)号：US20230044240A1

公开(公告)日：2023-02-09

申请号：US17970459

申请日：2022-10-20

Applicant: Micron Technology, Inc.

Inventor： Ching-Huang Lu ,  Vinh Q. Diep ,  Zhengyi Zhang ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30

Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

公开(公告)号：US20220336487A1

公开(公告)日：2022-10-20

申请号：US17301915

申请日：2021-04-19

Applicant: Micron Technology, Inc.

Inventor： Yifen Liu ,  Ching-Huang Lu ,  Shuangqiang Luo

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: An electronic device comprising first blocks and second blocks of an array comprising memory cells. The memory cells in the first and second blocks comprise memory pillars extending through a stack. The memory pillars comprise a charge blocking material laterally adjacent to the stack, a storage nitride material laterally adjacent to the charge blocking material, a tunnel dielectric material laterally adjacent to the storage nitride material, a channel material laterally adjacent to the tunnel dielectric material, and a fill material between opposing sides of the channel material. One or more of the storage nitride material and the tunnel dielectric material in the first blocks differ in thickness or in material composition from one or more of the storage nitride material and the tunnel dielectric material in the second blocks. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

公开(公告)号：US12300322B2

公开(公告)日：2025-05-13

申请号：US18103978

申请日：2023-01-31

Applicant: Micron Technology, Inc.

Inventor： Vinh Quang Diep ,  Jeffrey Ming-Hung Tsai ,  Ching-Huang Lu ,  Yingda Dong

IPC: G11C16/00 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34

Abstract: A memory device comprising a memory array and control logic operatively coupled with the memory array. The control logic is to: detect a program operation directed at a selected wordline of multiple wordlines of the memory array; determine, during an initial phase of the program operation, whether a program voltage being applied to the selected wordline satisfies a threshold program voltage; add, in response to the program voltage not satisfying the threshold program voltage, a base offset voltage to an initial pass voltage to generate a higher pass voltage, the initial pass voltage being a percentage of an initial program voltage; and cause the higher pass voltage to be applied to a remainder of the multiple wordlines other than the selected wordline.