公开(公告)号：US12080356B2

公开(公告)日：2024-09-03

申请号：US17876718

申请日：2022-07-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: G11C16/04 ,  G11C16/26

CPC classification number: G11C16/26 ,  G11C16/0483

Abstract: Methods of forming integrated circuit structures for a capacitive sense NAND memory include forming a first semiconductor overlying a dielectric, forming a second semiconductor to be in contact with a first end of the first semiconductor, forming a third semiconductor to be in contact with a second end of the first semiconductor opposite the first end of the first semiconductor, forming a vertical channel material structure overlying the first semiconductor and having a channel material capacitively coupled to the first semiconductor, and forming a plurality of series-connected field-effect transistors adjacent the vertical channel material structure.

公开(公告)号：US11903196B2

公开(公告)日：2024-02-13

申请号：US17127971

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Matthew J. King ,  Sidhartha Gupta ,  Paolo Tessariol ,  Kunal Shrotri ,  Kye Hyun Baek ,  Kyle A. Ritter ,  Shuji Tanaka ,  Umberto Maria Meotto ,  Richard J. Hill ,  Matthew Holland

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A microelectronic device comprises a stack structure comprising a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, strings of memory cells vertically extending through the block structures of the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, an additional stack structure vertically overlying the stack structure and comprising a vertical sequence of additional conductive structures and additional insulative structures arranged in additional tiers, first pillars extending through the additional stack structure and vertically overlying the strings of memory cells, each of the first pillars horizontally offset from a center of a corresponding string of memory cells, second pillars extending through the additional stack structure and vertically overlying the strings of memory cells, and additional slot structures comprising a dielectric material extending through at least a portion of the additional stack structure and sub-dividing each of the block structures into sub-block structures, the additional slot structures horizontally neighboring the first pillars. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US11678482B2

公开(公告)日：2023-06-13

申请号：US17557389

申请日：2021-12-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: H01L27/11556 ,  G11C5/02 ,  G11C5/06 ,  G11C16/34 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  G11C5/025 ,  G11C5/06 ,  G11C16/3427 ,  H01L27/11582

Abstract: Arrays of memory cells might include a first upper data line, a second upper data line, a lower data line, a first pass gate selectively connected to the lower data line, a second pass gate connected to the first pass gate and selectively connected to the lower data line, a third pass gate selectively connected to the lower data line, a fourth pass gate connected to the third pass gate and selectively connected to the lower data line, unit column structures selectively connected to a respective one of the upper data lines and capacitively coupled to a first channel of a respective one of the pass gates, and control lines capacitively coupled to a second channel of a respective one of the pass gates.

公开(公告)号：US20220383960A1

公开(公告)日：2022-12-01

申请号：US17876718

申请日：2022-07-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: G11C16/26 ,  G11C16/04

Abstract: Methods of forming integrated circuit structures for a capacitive sense NAND memory include forming a first semiconductor overlying a dielectric, forming a second semiconductor to be in contact with a first end of the first semiconductor, forming a third semiconductor to be in contact with a second end of the first semiconductor opposite the first end of the first semiconductor, forming a vertical channel material structure overlying the first semiconductor and having a channel material capacitively coupled to the first semiconductor, and forming a plurality of series-connected field-effect transistors adjacent the vertical channel material structure.

公开(公告)号：US11437106B2

公开(公告)日：2022-09-06

申请号：US17111729

申请日：2020-12-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: G11C11/04 ,  G11C16/26 ,  G11C16/04

Abstract: An array of memory cells might include a first data line, a second data line, a source, a capacitance selectively connected to the first data line, a string of series-connected non-volatile memory cells between the first data line and the capacitance, and a pass gate selectively connected between the second data line and the source, wherein an electrode of the capacitance is capacitively coupled to a channel of the pass gate.

公开(公告)号：US20220180939A1

公开(公告)日：2022-06-09

申请号：US17111770

申请日：2020-12-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/10

Abstract: Memory might include a non-volatile memory cell, a capacitance selectively connected to the non-volatile memory cell, a field-effect transistor having a channel capacitively coupled to an electrode of the capacitance, and a controller for access of the non-volatile memory cell configured to cause the memory to increase a voltage level of the electrode of the capacitance, selectively discharge the voltage level of the electrode of the capacitance through the non-volatile memory cell responsive to a data state stored in the non-volatile memory cell, and determine whether the field-effect transistor is activated in response to a remaining voltage level of the electrode of the capacitance.

公开(公告)号：US20180211710A1

公开(公告)日：2018-07-26

申请号：US15911910

申请日：2018-03-05

Applicant: Micron Technology, Inc.

Inventor： Masanobu Saito ,  Shuji Tanaka ,  Shinji Sato

IPC: G11C16/14 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  G11C16/26 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11524

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: Some embodiments include apparatuses and methods of using and forming such apparatuses. An apparatus among the apparatuses includes first and second conductive materials located in respective first and second levels of the apparatus, a pillar including a length extending between the first and second conductive materials, memory cells and control lines located along the pillar, a first select gate and a first select line located along the pillar between the first conductive material and the memory cells, a second select gate and a second select line located along the pillar between the first conductive material and the first select line, a first transistor and a first transistor gate line located along the pillar between the first conductive material and the first select line, and a second transistor and a second transistor gate line located along the pillar between the first conductive material and the first transistor.

公开(公告)号：US20240099007A1

公开(公告)日：2024-03-21

申请号：US18525652

申请日：2023-11-30

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Matthew J. King ,  Sidhartha Gupta ,  Paolo Tessariol ,  Kunal Shrotri ,  Kye Hyun Baek ,  Kyle A. Ritter ,  Shuji Tanaka ,  Umberto Maria Meotto ,  Richard J. Hill ,  Matthew Holland

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A microelectronic device comprises a stack structure comprising a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, strings of memory cells vertically extending through the block structures of the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, an additional stack structure vertically overlying the stack structure and comprising a vertical sequence of additional conductive structures and additional insulative structures arranged in additional tiers, first pillars extending through the additional stack structure and vertically overlying the strings of memory cells, each of the first pillars horizontally offset from a center of a corresponding string of memory cells, second pillars extending through the additional stack structure and vertically overlying the strings of memory cells, and additional slot structures comprising a dielectric material extending through at least a portion of the additional stack structure and sub-dividing each of the block structures into sub-block structures, the additional slot structures horizontally neighboring the first pillars. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US20220199641A1

公开(公告)日：2022-06-23

申请号：US17127971

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Matthew J. King ,  Sidhartha Gupta ,  Paolo Tessariol ,  Kunal Shrotri ,  Kye Hyun Baek ,  Kyle A. Ritter ,  Shuji Tanaka ,  Umberto Maria Meotto ,  Richard J. Hill ,  Matthew Holland

IPC: H01L27/11582 ,  H01L27/11556

Abstract: A microelectronic device comprises a stack structure comprising a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, strings of memory cells vertically extending through the block structures of the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, an additional stack structure vertically overlying the stack structure and comprising a vertical sequence of additional conductive structures and additional insulative structures arranged in additional tiers, first pillars extending through the additional stack structure and vertically overlying the strings of memory cells, each of the first pillars horizontally offset from a center of a corresponding string of memory cells, second pillars extending through the additional stack structure and vertically overlying the strings of memory cells, and additional slot structures comprising a dielectric material extending through at least a portion of the additional stack structure and sub-dividing each of the block structures into sub-block structures, the additional slot structures horizontally neighboring the first pillars. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US10354734B2

公开(公告)日：2019-07-16

申请号：US15911910

申请日：2018-03-05

Applicant: Micron Technology, Inc.

Inventor： Masanobu Saito ,  Shuji Tanaka ,  Shinji Sato

IPC: G11C16/06 ,  G11C16/14 ,  G11C16/26 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  G11C16/04 ,  G11C16/16 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  G11C16/10 ,  G11C16/30

Abstract: Some embodiments include apparatuses and methods of using and forming such apparatuses. An apparatus among the apparatuses includes first and second conductive materials located in respective first and second levels of the apparatus, a pillar including a length extending between the first and second conductive materials, memory cells and control lines located along the pillar, a first select gate and a first select line located along the pillar between the first conductive material and the memory cells, a second select gate and a second select line located along the pillar between the first conductive material and the first select line, a first transistor and a first transistor gate line located along the pillar between the first conductive material and the first select line, and a second transistor and a second transistor gate line located along the pillar between the first conductive material and the first transistor.