公开(公告)号：US20180261264A1

公开(公告)日：2018-09-13

申请号：US15978578

申请日：2018-05-14

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Harish N. Venkata ,  Guy S. Perry

IPC: G11C7/10 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G11C7/1006 ,  G11C7/1036 ,  G11C11/4091 ,  G11C11/4096 ,  G11C2211/4013

Abstract: The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component having a first storage location and a second storage location associated therewith. A controller is coupled to the sensing circuitry. The controller is configured to control an amount of power associated with shifting a data value stored in the first storage location to the second storage location by applying a charge sharing operation.

公开(公告)号：US20180254071A1

公开(公告)日：2018-09-06

申请号：US15972783

申请日：2018-05-07

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Harish N. Venkata ,  Guy S. Perry

IPC: G11C7/06 ,  G11C7/12 ,  G11C7/10 ,  G11C8/10 ,  G11C7/22

CPC classification number: G11C7/065 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/222 ,  G11C8/10 ,  G11C11/403 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

Abstract: The present disclosure includes apparatuses and methods related to storing a data value in a sensing circuitry element. An example method comprises sensing a first data value with a sense amplifier of a sensing circuitry element, moving a second data value from a first storage location of a compute component to a second storage location of the compute component, and storing, in the first storage location, a third data value resulting from a logical operation performed on the first data value and the second data value. The logical operation can be performed by logic circuitry of the sensing circuitry element.

公开(公告)号：US10013197B1

公开(公告)日：2018-07-03

申请号：US15611369

申请日：2017-06-01

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Gary L. Howe ,  Harish N. Venkata

IPC: G11C7/00 ,  G06F3/06 ,  G11C7/08 ,  G11C7/10

CPC classification number: G06F3/0635 ,  G06F3/0611 ,  G06F3/0625 ,  G06F3/0683 ,  G11C7/08 ,  G11C7/1006 ,  G11C7/1009 ,  G11C7/1012 ,  G11C7/1036 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C17/16

Abstract: The present disclosure includes apparatuses and methods related to a shift skip. An example apparatus comprises a plurality of sensing circuitries, comprising respective sense amplifiers and respective compute components. A controller is configured to, responsive to a mask data unit associated with a first sensing circuitry having a particular value, cause a data value to be shifted from a second sensing circuitry to a third sensing circuitry without shifting the data value to the first sensing circuitry, wherein the first sensing circuitry is physically located between the second sensing circuitry and the third sensing circuitry.

公开(公告)号：US09972367B2

公开(公告)日：2018-05-15

申请号：US15216440

申请日：2016-07-21

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Harish N. Venkata ,  Guy S. Perry

IPC: G11C7/08

CPC classification number: G11C7/1006 ,  G11C7/1036 ,  G11C11/4091 ,  G11C11/4096 ,  G11C2211/4013

Abstract: The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component having a first storage location and a second storage location associated therewith. A controller is coupled to the sensing circuitry. The controller is configured to control an amount of power associated with shifting a data value stored in the first storage location to the second storage location by applying a charge sharing operation.

公开(公告)号：US20180025758A1

公开(公告)日：2018-01-25

申请号：US15693064

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Harish N. Venkata ,  Guy S. Perry

IPC: G11C7/06 ,  G11C8/10 ,  G11C7/12 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C7/065 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/222 ,  G11C8/10 ,  G11C11/403 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

Abstract: The present disclosure includes apparatuses and methods related to storing a data value in a sensing circuitry element. An example method comprises sensing a first data value with a sense amplifier of a sensing circuitry element, moving a second data value from a first storage location of a compute component to a second storage location of the compute component, and storing, in the first storage location, a third data value resulting from a logical operation performed on the first data value and the second data value. The logical operation can be performed by logic circuitry of the sensing circuitry element.

公开(公告)号：US11132142B2

公开(公告)日：2021-09-28

申请号：US17063463

申请日：2020-10-05

Applicant: Micron Technology, Inc.

Inventor： Byung S. Moon ,  Harish N. Venkata ,  Gary L. Howe ,  Myung Ho Bae

IPC: G11C7/20 ,  G06F3/06 ,  G11C11/4072 ,  G11C8/04 ,  G11C7/10 ,  G06F11/10 ,  G11C29/52 ,  G11C29/02 ,  G11C29/46

Abstract: A memory device may include a first wordline and a second wordline, each having multiple memory cells. The memory device may also include control circuitry to facilitate writing a data pattern to the memory cells of the first wordline and facilitate copying the data pattern from the first wordline to the second wordline. Copying the first wordline to the second wordline may include activating the second wordline such that the first wordline and the second wordline are simultaneously active. A memory cell of the first wordline may be written a data value of the data pattern, and the memory cell may drive, at least partially, a corresponding memory cell of the second wordline with the data value.

公开(公告)号：US11087820B2

公开(公告)日：2021-08-10

申请号：US16556763

申请日：2019-08-30

Applicant: Micron Technology, Inc.

Inventor： Yu-Feng Chen ,  Byung S. Moon ,  Myung Ho Bae ,  Harish N. Venkata

IPC: G11C11/4074 ,  G11C11/408 ,  G06F13/42 ,  G11C11/4094 ,  G11C8/12

Abstract: A memory device may include a memory array comprising at least two sections. Each of the sections may further include multiple memory cells. The memory device may also include one or more controllers designed to receive one or more commands to initiate writing logical data to the multiple memory cells of a first section and a second section. Additionally, the writing may alternate between the first section and the second section until the first section and second section have been entirely written with the logical data.

公开(公告)号：US20210019075A1

公开(公告)日：2021-01-21

申请号：US17063463

申请日：2020-10-05

Applicant: Micron Technology, Inc.

Inventor： Byung S. Moon ,  Harish N. Venkata ,  Gary L. Howe ,  Myung Ho Bae

IPC: G06F3/06 ,  G11C11/4072 ,  G11C7/20 ,  G11C8/04 ,  G11C7/10 ,  G06F11/10

Abstract: A memory device may include a first wordline and a second wordline, each having multiple memory cells. The memory device may also include control circuitry to facilitate writing a data pattern to the memory cells of the first wordline and facilitate copying the data pattern from the first wordline to the second wordline. Copying the first wordline to the second wordline may include activating the second wordline such that the first wordline and the second wordline are simultaneously active. A memory cell of the first wordline may be written a data value of the data pattern, and the memory cell may drive, at least partially, a corresponding memory cell of the second wordline with the data value.

公开(公告)号：US10825491B2

公开(公告)日：2020-11-03

申请号：US15837666

申请日：2017-12-11

Applicant: Micron Technology, Inc.

Inventor： Byung S. Moon ,  Gary L. Howe ,  Harish N. Venkata ,  David R. Brown

IPC: G11C7/10 ,  G11C11/4072 ,  G11C8/04 ,  G11C11/408 ,  G11C7/20 ,  G06F12/06 ,  G06F11/10 ,  G11C29/52 ,  G11C29/02 ,  G11C29/46

Abstract: A memory device may include a memory array, which may also include, multiple memory cells. The memory device may also include one or more counters designed to generate internal memory addresses to sequentially access the memory cells and facilitate writing logical zeros to all of the memory cells.

公开(公告)号：US10795603B2

公开(公告)日：2020-10-06

申请号：US16555852

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Byung S. Moon ,  Harish N. Venkata ,  Gary L. Howe ,  Myung Ho Bae

IPC: G06F3/06 ,  G11C11/4072 ,  G11C7/20 ,  G11C8/04 ,  G11C7/10 ,  G06F11/10 ,  G11C29/52 ,  G11C29/02 ,  G11C29/46

Abstract: A memory device may include a memory array that includes multiple memory cells. The memory device may also include multiple sense amplifiers that, in operation, may each be connected to one or more memory cells. The sense amplifiers may be designed to assist in writing logical zeros to the multiple memory cells.