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公开(公告)号：US10957402B2
公开(公告)日：2021-03-23
申请号：US16259610
申请日：2019-01-28
Applicant: Micron Technology, Inc.
Inventor： Shigekazu Yamada
Abstract: Discussed herein are systems and methods for compensating degradation of a transistor in a high-voltage (HV) shifter configured to transfer an input voltage to an access line, such as a global wordline. An embodiment of a memory device comprises a group of memory cells, and a HV shifter circuit including a signal transfer circuit and a compensator circuit. The signal transfer circuit includes a P-channel transistor to transfer a high-voltage input to an access line. The compensator circuit can provide a control signal to the signal transfer circuit by coupling a support voltage higher than a supply voltage (Vcc) to the signal transfer circuit for a specified time period to compensate for degradation of the P-channel transistor. The transferred high voltage is used to charge the access line to selectively read, program, or erase memory cells.
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公开(公告)号：US10937501B2
公开(公告)日：2021-03-02
申请号：US16574669
申请日：2019-09-18
Applicant: Micron Technology, Inc.
Inventor： Shigekazu Yamada
IPC: G11C16/08 , G11C16/30 , G11C16/04 , G11C16/14 , G11C16/26 , G11C16/10 , G11C5/14 , G11C16/32 , G11C11/56
Abstract: Discussed herein are systems and methods for charging an access line to a nonvolatile memory cell during a standby state, such as to prevent or mitigate standby-state charge loss. An embodiment of a memory device comprises a memory cell, a string driver circuit, and a charging circuit. The string driver circuit is coupled to the memory cell via a local word line, and has a common p-well. The charging circuit, in response to a voltage of a global word line of the memory device falling below a reference voltage during a standby state, couple a supply voltage to the common p-well of the string driver circuit to charge the global word line to a positive bias potential. The memory device includes a leakage compensation circuit to compensate for the junction leakage.
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公开(公告)号：US10803957B2
公开(公告)日：2020-10-13
申请号：US16716043
申请日：2019-12-16
Applicant: Micron Technology, Inc.
Inventor： Shigekazu Yamada
Abstract: Discussed herein are systems and methods for charging a bit line (BL) during programming of non-volatile memory cells. An embodiment of a memory device comprises a group of memory cells including a first memory cell coupled to a first BL and a second memory cell coupled to a second BL, and a BL charging circuit that provides an inhibit signal to the second BL in response to a control signal to program the first memory cell. To provide the inhibit signal, the BL charging circuit apply a supply voltage to the second BL for an initial wait time and, after the initial wait time, apply a higher voltage than the supply voltage, until the inhibit signal reaches a value of the supply voltage. The first memory cells is programmed in response to the established voltage on the second BL.
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公开(公告)号：US20200243142A1
公开(公告)日：2020-07-30
申请号：US16813273
申请日：2020-03-09
Applicant: Micron Technology, Inc.
Inventor： Shigekazu Yamada
Abstract: Discussed herein are systems and methods for protecting against transistor degradation in a high-voltage (HV) shifter to transfer an input voltage to an access line, such as a global wordline. An embodiment of a memory device comprises memory cells and a HV shifter circuit that includes a signal transfer circuit, and first and second HV control circuits. The signal transfer circuit includes a P-channel transistor to transfer a high-voltage input to an access line. The first HV control circuit couples a bias voltage to the P-channel transistor for a first time period, and the second HV control circuit couples a stress-relief signal to the P-channel transistor for a second time period, after the first time period, to reduce degradation of the P-channel transistor. The transferred high voltage can be used to charge the access line to selectively read, program, or erase memory cells.
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45.发明申请公开(公告)号：US20200234781A1
公开(公告)日：2020-07-23
申请号：US16694043
申请日：2019-11-25
Applicant: Micron Technology, Inc.
Inventor： Han Zhao , Akira Goda , Krishna K. Parat , Aurelio Giancarlo Mauri , Haitao Liu , Toru Tanzawa , Shigekazu Yamada , Koji Sakui
Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.
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Patent Agency Ranking
公开(公告)号：US10706912B2
公开(公告)日：2020-07-07
申请号：US16710006
申请日：2019-12-11
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Shigekazu Yamada
IPC: G11C16/14 , G11C11/4091 , G11C7/10 , G11C7/18 , G11C7/08 , G11C7/12 , G11C7/22 , G11C11/4094 , G11C11/16 , G11C7/06 , G11C16/28 , G11C16/16 , G11C16/32 , G11C16/26 , G11C16/24
Abstract: Memory might include control logic configured to apply an erase pulse to a data line and to a common source concurrently with applying a higher second voltage level to a control gate of a transistor connected between the data line and the common source, concurrently discharge the voltage level of the data line and the voltage level of the common source, monitor a representation of a voltage difference between the voltage level of the data line and the voltage level of the control gate of the transistor, activate a current path between the control gate of the transistor and the common source in response to the voltage difference being deemed to be greater than a first value, and deactivate the current path between the control gate of the transistor and the common source in response to the voltage difference being deemed to be less than a second value.
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公开(公告)号：US20200211661A1
公开(公告)日：2020-07-02
申请号：US16390558
申请日：2019-04-22
Applicant: Micron Technology, Inc.
Inventor： Michele Piccardi , Xiaojiang Guo , Shigekazu Yamada
Abstract: Devices and techniques are disclosed herein to provide a high-voltage bias signal in a standby state of the storage system without exceeding a limited maximum standby current allowance of the storage system. The high-voltage bias signal can enable a string driver circuit in the standby state to couple a global word line to a local word line, to provide a bias to, or sink a voltage from, a pillar of a string of memory cells of the storage system in the standby state, such as to reduce read disturbances in the storage system.
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48.发明申请公开(公告)号：US20200118615A1
公开(公告)日：2020-04-16
申请号：US16710006
申请日：2019-12-11
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Shigekazu Yamada
IPC: G11C11/4091 , G11C16/24 , G11C16/14 , G11C7/10 , G11C7/18 , G11C7/08 , G11C7/12 , G11C7/22 , G11C11/4094 , G11C11/16 , G11C7/06 , G11C16/28 , G11C16/16 , G11C16/32 , G11C16/26
Abstract: Memory might include control logic configured to apply an erase pulse to a data line and to a common source concurrently with applying a higher second voltage level to a control gate of a transistor connected between the data line and the common source, concurrently discharge the voltage level of the data line and the voltage level of the common source, monitor a representation of a voltage difference between the voltage level of the data line and the voltage level of the control gate of the transistor, activate a current path between the control gate of the transistor and the common source in response to the voltage difference being deemed to be greater than a first value, and deactivate the current path between the control gate of the transistor and the common source in response to the voltage difference being deemed to be less than a second value.
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公开(公告)号：US10591541B2
公开(公告)日：2020-03-17
申请号：US16101563
申请日：2018-08-13
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Shigekazu Yamada
IPC: G01R31/3177 , G01R31/317 , G11C29/38
Abstract: A device includes a comparator, a reference signal node electrically coupled to a first input of the comparator, a plurality of test signal nodes, a plurality of first select signal nodes, a first multiplexer coupled between the plurality of test signal nodes and the comparator, a plurality of latches, a plurality of second select signal nodes, and a second multiplexer. Each first select signal node corresponds to a test signal node. The first multiplexer electrically couples one of the plurality of test signal nodes to a second input of the comparator in response to a corresponding first select signal. Each latch corresponds to a test signal node. Each second select signal node corresponds to a latch. The second multiplexer electrically couples the output of the comparator to an input of one of the plurality of latches in response to a corresponding second select signal.
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公开(公告)号：US10510419B1
公开(公告)日：2019-12-17
申请号：US16021998
申请日：2018-06-28
Applicant: Micron Technology, Inc.
Inventor： Shigekazu Yamada
Abstract: Discussed herein are systems and methods for charging a bit line (BL) during programming of non-volatile memory cells. An embodiment of a memory device comprises a group of memory cells including a first memory cell coupled to a first BL and a second memory cell coupled to a second BL, and a BL charging circuit that provides an inhibit signal to the second BL in response to a control signal to program the first memory cell. To provide the inhibit signal, the BL charging circuit apply a supply voltage to the second BL for an initial wait time and, after the initial wait time, apply a higher voltage than the supply voltage, until the inhibit signal reaches a value of the supply voltage. The first memory cells is programmed in response to the established voltage on the second BL.
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