公开(公告)号：US11386946B2

公开(公告)日：2022-07-12

申请号：US16513400

申请日：2019-07-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi ,  Donald M. Morgan

IPC: G11C11/406 ,  G06F9/30 ,  G11C16/34 ,  G11C11/16

Abstract: Apparatuses and methods for tracking all row accesses in a memory device over time may be used to identify rows which are being hammered so that ‘victim’ rows may be identified and refreshed. A register stack may include a number of count values, each of which may track a number of accesses to a portion of the word lines of the memory device. Anytime a row within a given portion is accessed, the associated count value may be incremented. When a count value exceeds a first threshold, a second stack with a second number of count values may be used to track numbers of accesses to sub-portions of the given portion. When a second count value exceeds a second threshold, victim addresses may be provided to refresh the victim word lines associated with any of the word lines within the sub-portion.

公开(公告)号：US11211110B1

公开(公告)日：2021-12-28

申请号：US17005275

申请日：2020-08-27

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi ,  Donald M. Morgan

IPC: G11C11/40 ,  G11C11/406 ,  G06F7/58 ,  G11C11/4072 ,  G11C11/408

Abstract: A volatile memories includes an address scrambler configured to scramble at least a portion of a received addresses to obscure address topography of a memory array using at least one scramble key. The at least one scramble key is generated by a random number generator. The address scrambler is configured to perform logical bitwise operations using between a received address and the at least one scramble key to generate the scrambled row address.

公开(公告)号：US20210158851A1

公开(公告)日：2021-05-27

申请号：US17170616

申请日：2021-02-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi ,  Raghukiran Sreeramaneni

IPC: G11C11/408 ,  G11C11/406 ,  G11C11/16 ,  G11C11/4074 ,  G11C15/04

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for analog row access rate determination. Accesses to different row addresses may be tracked by storing one or more received addresses in a slice of stack. Each slice includes an accumulator circuit which provides a voltage based on charge on a capacitor. When a row address is received, it may be compared to the row addresses stored in the stack, and if there is a match, the charge on the capacitor in the associated accumulator circuit is increased. Each slice may also include a voltage to time (VtoT) circuit which may be used to identify the highest of the voltages provided by the accumulator circuits. The row address stored in the slide with the highest voltage may be refreshed.

公开(公告)号：US10984886B2

公开(公告)日：2021-04-20

申请号：US16811717

申请日：2020-03-06

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi

IPC: G11C29/00 ,  H03K19/20

Abstract: A memory device includes a memory bank accessible via a plurality of memory addresses. The memory device further includes a fuse array including a plurality of fuse banks. A fuse bank of the plurality of fuse banks includes a fuse circuit, which includes a fuse latch having first input circuitry. The fuse latch is implemented to store a first bit of a first memory address received at the first input circuitry. The fuse circuit also includes a matching circuit coupled to the first input circuitry. The matching circuit is implemented to receive a first bit of a second memory address at the first input circuitry and to output, at output circuitry, a comparison result based at least in part on the first bit of the first memory address and the first bit of the second memory address.

公开(公告)号：US20210057012A1

公开(公告)日：2021-02-25

申请号：US16548027

申请日：2019-08-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi ,  Raghukiran Sreeramaneni

IPC: G11C11/408 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/16 ,  G11C15/04

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for analog row access rate determination. Accesses to different row addresses may be tracked by storing one or more received addresses in a slice of stack. Each slice includes an accumulator circuit which provides a voltage based on charge on a capacitor. When a row address is received, it may be compared to the row addresses stored in the stack, and if there is a match, the charge on the capacitor in the associated accumulator circuit is increased. Each slice may also include a voltage to time (VtoT) circuit which may be used to identify the highest of the voltages provided by the accumulator circuits. The row address stored in the slide with the highest voltage may be refreshed.

公开(公告)号：US09508409B2

公开(公告)日：2016-11-29

申请号：US14254378

申请日：2014-04-16

Applicant: Micron Technology, Inc.

Inventor： Mark K. Hadrick ,  Jeffrey P. Wright ,  Victor Wong ,  Simon J. Lovett ,  Donald M. Morgan ,  William F. Jones ,  Sujeet Ayyapureddi ,  Dean D. Gans ,  Jongtae Kwak

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/12

CPC classification number: G11C7/22 ,  G11C7/1009 ,  G11C7/1042 ,  G11C8/12 ,  G11C2207/229

Abstract: Apparatuses and methods for implementing masked write commands are disclosed herein. An example apparatus may include a memory bank, a local buffer circuit, and an address control circuit. The local buffer circuit may be associated with the memory bank. The address control circuit may be coupled to the memory bank and configured to receive a command and an address associated with the command. The address control circuit may include a global buffer circuit configured to store the address. The address control circuit may further be configured to delay the command using one of a plurality of command paths based, at least in part, on a write latency and to provide the address stored in the global buffer circuit to the local buffer circuit to be stored therein.

Abstract translation: 本文公开了用于实现屏蔽写入命令的装置和方法。 示例性装置可以包括存储体，局部缓冲电路和地址控制电路。 本地缓冲电路可以与存储体相关联。 地址控制电路可以耦合到存储体并被配置为接收命令和与该命令相关联的地址。 地址控制电路可以包括被配置为存储地址的全局缓冲电路。 地址控制电路还可以被配置为至少部分地基于写等待时间来延迟使用多个命令路径之一的命令，并且将存储在全局缓冲器电路中的地址提供给要存储的本地缓冲器电路 其中。

公开(公告)号：US20150356047A1

公开(公告)日：2015-12-10

申请号：US14297864

申请日：2014-06-06

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi ,  Don Morgan ,  Myung Gyoo Won

IPC: G06F13/42 ,  H03M13/05

CPC classification number: G06F13/4221 ,  H03M5/145 ,  H03M13/05 ,  H03M13/31

Abstract: Apparatuses and methods for performing a data bus inversion operation (DBI) are described. An example apparatus includes a DBI circuit configured to, in parallel, determine preliminary DBI bits based on a block of data. Individual preliminary DBI bits are associated with respective sub-blocks of the block of data. The DBI circuit is further configured to serially determine DBI bits based on the preliminary DBI bits. Individual ones of the DBI bits are associated with respective ones of the sub-blocks. The DBI circuit is further configured to invert bits of individual sub-blocks responsive to the respective associated DBI bits having a particular logical value to provide DBI data. The apparatus further includes data outputs configured to serially output sub-blocks of the DBI data and the DBI bits.

Abstract translation: 描述了用于执行数据总线反转操作（DBI）的装置和方法。 一个示例性设备包括一个DBI电路，被配置为并行地基于数据块来确定初始DBI位。 单独的初始DBI位与数据块的相应子块相关联。 DBI电路还被配置为基于初始DBI位串行确定DBI位。 DBI位中的各个与相应的子块相关联。 DBI电路还被配置为响应于具有特定逻辑值的相应的相关联的DBI位来反转各个子块的比特以提供DBI数据。 该装置还包括被配置为串行地输出DBI数据和DBI比特的子块的数据输出。

公开(公告)号：US12292798B2

公开(公告)日：2025-05-06

申请号：US17822915

申请日：2022-08-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi

IPC: G06F11/00 ,  G06F11/10

Abstract: Apparatuses, systems, and methods for module level error correction. Multiple memory devices a packaged together in a memory module. The module includes a module error correction code (ECC) circuit which pools information multiple memory devices on the module. In an example read operation, multiple memory devices each provide a codeword which includes data bits and parity bits. The codewords may include data bits provided along a data bus and parity bits provided along a parity bus. The ECC circuit pools the codewords and detects errors in the pooled codewords.

公开(公告)号：US20250112643A1

公开(公告)日：2025-04-03

申请号：US18747696

申请日：2024-06-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi

IPC: H03M13/11 ,  H03M13/00

Abstract: Apparatuses, systems, and methods for scalable 1-pass error correction code operations. A memory device includes an error correction code (ECC) circuit which generates a number of parity bits based on a plurality of data bits during a write operation. The number of parity bits may be selected based on a setting in a mode register. The data and parity are written to the memory array as part of a single access pass. The data may be written to a selected portion of the data column planes, while the parity is written to one or more column planes of the extra column plane or a non-selected portion of the data column planes.

公开(公告)号：US20250110643A1

公开(公告)日：2025-04-03

申请号：US18747658

申请日：2024-06-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi

IPC: G06F3/06

Abstract: Apparatuses, systems, and methods for bounded fault compliant metadata storage. A memory module may be capable of repairing information along a portion of the data terminals of a memory device. To prevent errors in the metadata from propagating across more than the correctable portion, the metadata may be provided along a portion of the data terminals, while the data associated with that metadata is provided along more data terminals. For example, in a 9×2p2 module the data may use two terminals, while the metadata only uses one. In a 5×2p4 module, the metadata may use a pair of terminals, while the data uses four.