中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

57 records (took 0.021 seconds)

    PICK AND PLACE TAPE RELEASE FOR THIN SEMICONDUCTOR DIES
    41.
    发明申请
    PICK AND PLACE TAPE RELEASE FOR THIN SEMICONDUCTOR DIES 有权
    用于半导体芯片的拾取和放置磁带释放

    公开(公告)号：US20130039733A1

    公开(公告)日：2013-02-14

    申请号：US13207609

    申请日：2011-08-11

    Applicant: Bucknell C. Webb

    Inventor： Bucknell C. Webb

    IPC: H01L21/67 ,  B25J11/00

    CPC classification number: H01L21/67132

    Abstract: Pick and place tape release techniques and tools that allow thin, fragile semiconductor dies to be removed from wafer tape with reduced tape release forces applied to the semiconductor dies. For example, a method for removing semiconductor die from wafer tape includes mounting a wafer ring having wafer tape and one or more dies attached to the wafer tape, and aligning an ejector pin assembly under a target die to be removed from the wafer tape. The ejector pin assembly includes a vacuum housing, an ejector pin, a suction plate, and an aperture formed in the suction plate in alignment with the ejector pin. A vacuum is generated in the vacuum housing to draw the tape against a surface of the suction plate. The ejector pin is extended through the vacuum housing out from the aperture of the suction plate to push against a backside of the target die and release the tape from the backside of the target die, and as the tape is released from the backside of the target die, the tape is drawn down against the suction plate by suction force of the vacuum.

    Abstract translation: 拾取和放置磁带释放技术和工具，其允许薄的，脆弱的半导体管芯从晶片带去除，同时减小施加到半导体管芯上的剥离力。 例如，从晶片带除去半导体管芯的方法包括安装具有晶片带的晶片环和安装在晶片带上的一个或多个管芯，以及使靶组件下方的顶针组件对准晶片带。 顶针组件包括真空壳体，顶针，吸板和形成在吸板中的与顶针对准的孔。 在真空壳体中产生真空以将带材吸附在吸盘的表面上。 顶针从吸板的孔径延伸穿过真空壳体，以推压目标管芯的背面并从目标管芯的背面释放带，并且当带从靶的背面释放时 模具，胶带通过真空的吸力被吸引到吸盘上。

    COOLING DEVICE WITH A PREFORMED COMPLIANT INTERFACE
    42.
    发明申请
    COOLING DEVICE WITH A PREFORMED COMPLIANT INTERFACE 审中-公开

    公开(公告)号：US20090294955A1

    公开(公告)日：2009-12-03

    申请号：US12538123

    申请日：2009-08-08

    Applicant: Bucknell C. Webb

    Inventor： Bucknell C. Webb

    IPC: H01L23/34

    CPC classification number: H01L23/433 ,  H01L2924/0002 ,  H05K7/20472 ,  Y10T29/49117 ,  H01L2924/00

    Abstract: An integrated circuit package includes: a substrate; an electronic circuit located on the substrate, the electronic circuit comprising a topography of at least one level; a cooling device located over the electronic circuit; a compliant interface disposed between the electronic circuit and the cooling device, wherein the compliant interface comprises a first surface and a second surface and wherein the first surface is in thermal contact with the electronic circuit, and wherein the compliant interface is preformed from a compliant material such that the first surface substantially conforms to the topography of the electronic circuit.

    COOLING DEVICE WITH A PREFORMED COMPLIANT INTERFACE
    43.
    发明申请
    COOLING DEVICE WITH A PREFORMED COMPLIANT INTERFACE 有权
    具有预先配合接口的冷却装置

    公开(公告)号：US20090027860A1

    公开(公告)日：2009-01-29

    申请号：US11781854

    申请日：2007-07-23

    Applicant: Bucknell C. Webb

    Inventor： Bucknell C. Webb

    IPC: H05K7/20 ,  F28F3/02 ,  H01R43/00

    CPC classification number: H01L23/433 ,  H01L2924/0002 ,  H05K7/20472 ,  Y10T29/49117 ,  H01L2924/00

    Abstract: An integrated circuit package includes: a substrate; an electronic circuit located on the substrate, the electronic circuit comprising a topography of at least one level; a cooling device located over the electronic circuit; a compliant interface disposed between the electronic circuit and the cooling device, wherein the compliant interface comprises a first surface and a second surface and wherein the first surface is in thermal contact with the electronic circuit, and wherein the compliant interface is preformed from a compliant material such that the first surface substantially conforms to the topography of the electronic circuit.

    Abstract translation: 集成电路封装包括：衬底; 位于所述基板上的电子电路，所述电子电路包括至少一个电平的形貌; 位于电子电路上方的冷却装置; 设置在所述电子电路和所述冷却装置之间的兼容接口，其中所述柔性接口包括第一表面和第二表面，并且其中所述第一表面与所述电子电路热接触，并且其中所述柔性接口由柔性材料 使得第一表面基本上符合电子电路的形貌。

    Compliant thermal interface structure with vapor chamber
    44.
    发明授权
    Compliant thermal interface structure with vapor chamber 失效
    符合蒸汽室的热界面结构

    公开(公告)号：US07264041B2

    公开(公告)日：2007-09-04

    申请号：US11151831

    申请日：2005-06-14

    Applicant: John P. Karidis ,  Mark Schultz ,  Bucknell C. Webb

    Inventor： John P. Karidis ,  Mark Schultz ,  Bucknell C. Webb

    IPC: F28D15/02

    CPC classification number: H01L23/427 ,  H01L23/433 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A structure for cooling an electronic device is disclosed. The structure includes a top layer disposed over the electronic device. The structure further includes a plurality of spring elements disposed between the top layer and the electronic device, wherein at least one spring element comprises a spring portion, provides a heat path from the electronic device and provides mechanical compliance. The structure further includes a seal for containing a space between the top layer and the electronic device, wherein the space contained includes the plurality of spring elements, and a liquid with vaporizing capability disposed with the space contained.

    Abstract translation: 公开了一种用于冷却电子设备的结构。 该结构包括设置在电子设备上的顶层。 该结构还包括设置在顶层和电子设备之间的多个弹簧元件，其中至少一个弹簧元件包括弹簧部分，提供来自电子设备的热路径并提供机械顺应性。 该结构还包括用于在顶层和电子设备之间容纳空间的密封件，其中容纳的空间包括多个弹簧元件，以及具有包含空间的蒸发能力的液体。

    Method and apparatus for determining systematic errors
    45.
    发明授权
    Method and apparatus for determining systematic errors 失效
    用于确定系统误差的方法和装置

    公开(公告)号：US5901003A

    公开(公告)日：1999-05-04

    申请号：US628910

    申请日：1996-04-08

    Applicant: Timothy Joseph Chainer ,  Anthony Paul Praino ,  Mark Delorman Schultz ,  Bucknell C. Webb ,  Edward John Yarmchuk

    Inventor： Timothy Joseph Chainer ,  Anthony Paul Praino ,  Mark Delorman Schultz ,  Bucknell C. Webb ,  Edward John Yarmchuk

    IPC: G11B5/55 ,  G11B5/596 ,  G11B19/04 ,  G11B21/10 ,  G11B5/09

    CPC classification number: G11B19/04 ,  G11B21/106 ,  G11B5/5565 ,  G11B5/59633

    Abstract: Improvements in placement of timing patterns in self servo writing include correcting for random and systematic errors due to geometric effects. In a disk drive having a recording head with separate read and write elements, a method for determining separation between the elements and for correcting for such errors as a function of skew angle between the head and the disk. Errors resulting from misalignment and non-parallelism of the elements as well as misalignment of the head on it its actuator are also detected and corrected. Errors due to changes in rotational velocity of the disk and misplacement of timing patterns with respect to adjacent timing patterns are detected and corrected. In general, a single revolution process may be used to both write and detect random errors on each track and corrected on subsequent tracks.

    Abstract translation: 自动写入中定时模式布置的改进包括纠正由于几何效应引起的随机和系统误差。 在具有具有分离的读取和写入元件的记录头的磁盘驱动器中，确定元件之间的间隔并用于校正这种错误的方法，其作为头部和盘之间的歪斜角的函数。 元件的不对准和不平行度导致的误差以及头部在其致动器上的未对准性也被检测和校正。 检测并纠正由于盘的旋转速度的变化引起的错误和定时图案相对于相邻的定时图案的错位。 通常，可以使用单次旋转处理来写入和检测每个轨道上的随机误差并在随后的轨道上进行校正。

    Semiconductor trench inductors and transformers
    47.
    发明授权
    Semiconductor trench inductors and transformers 有权
    半导体沟槽电感和变压器

    公开(公告)号：US08686522B2

    公开(公告)日：2014-04-01

    申请号：US13272485

    申请日：2011-10-13

    Applicant: Bucknell C. Webb

    Inventor： Bucknell C. Webb

    IPC: H01L29/82 ,  H01L21/02

    CPC classification number: H01L23/645 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Semiconductor trench inductor and transformer structures are provided, which include thin film conductive layers and magnetic layers formed within trenches etched in semiconductor substrates. Semiconductor trench devices effectively provide vertical oriented inductor and transformer structures whereby conductive coils and magnetic layers are vertically oriented on edge within trenches, thereby providing a space-saving compact design, and which allows the conductive layers within the trench to be enclosed by magnetic material, thereby providing a density of magnetic material that increases the storable energy density.

    Abstract translation: 提供半导体沟槽电感器和变压器结构，其包括形成在半导体衬底中蚀刻的沟槽内的薄膜导电层和磁性层。 半导体沟槽器件有效地提供垂直取向的电感器和变压器结构，由此导电线圈和磁性层在沟槽内的边缘垂直取向，从而提供节省空间的紧凑设计，并且允许沟槽内的导电层被磁性材料包围， 从而提供增加可储存能量密度的磁性材料的密度。

    INDUCTOR WITH STACKED CONDUCTORS
    48.
    发明申请
    INDUCTOR WITH STACKED CONDUCTORS 有权
    带导体的电感器

    公开(公告)号：US20130314192A1

    公开(公告)日：2013-11-28

    申请号：US13477978

    申请日：2012-05-22

    Applicant: Robert E. Fontana, JR. ,  Philipp Herget ,  Eugene J. O'Sullivan ,  Lubomyr T. Romankiw ,  Naigang Wang ,  Bucknell C. Webb

    Inventor： Robert E. Fontana, JR. ,  Philipp Herget ,  Eugene J. O'Sullivan ,  Lubomyr T. Romankiw ,  Naigang Wang ,  Bucknell C. Webb

    IPC: H01F27/28

    CPC classification number: H01F27/2804 ,  H01F5/00 ,  H01F17/0013 ,  H01F2017/0066 ,  H01F2017/0086 ,  H01F2027/2809 ,  H01L28/10

    Abstract: A thin film coupled inductor, a thin film spiral inductor, and a system that includes an electronic device and a power supply or power converter incorporating one or more such inductors. A thin film coupled inductor includes a wafer substrate; a bottom yoke comprising a magnetic material above the wafer substrate; a first insulating layer above the bottom yoke; a first conductor above the bottom yoke and separated therefrom by the first insulating layer; a second insulating layer above the first conductor; a second conductor above the second insulating layer; a third insulating layer above the second conductor; and a non-planar top yoke above the third insulating layer, the top yoke comprising a magnetic material.

    Abstract translation: 薄膜耦合电感器，薄膜螺旋电感器以及包括电子器件和并入一个或多个此类电感器的电源或功率转换器的系统。 薄膜耦合电感器包括晶片衬底; 底部轭，其包括晶片衬底上方的磁性材料; 在底部轭上方的第一绝缘层; 第一导体，位于底部磁轭之上并由第一绝缘层分离; 在所述第一导体上方的第二绝缘层; 在第二绝缘层上方的第二导体; 在第二导体上方的第三绝缘层; 以及在第三绝缘层上方的非平面顶部磁轭，顶部磁轭包括磁性材料。

Patent Agency Ranking