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    UNDERFILL MATERIAL DISPENSING FOR STACKED SEMICONDUCTOR CHIPS
    3.
    发明申请
    UNDERFILL MATERIAL DISPENSING FOR STACKED SEMICONDUCTOR CHIPS 有权
    堆叠半导体芯片的材料分配

    公开(公告)号：US20140013606A1

    公开(公告)日：2014-01-16

    申请号：US13567567

    申请日：2012-08-06

    Applicant: Jae-Woong Nah ,  Katsuyuki Sakuma ,  Bucknell C. Webb

    Inventor： Jae-Woong Nah ,  Katsuyuki Sakuma ,  Bucknell C. Webb

    IPC: B43L7/00

    CPC classification number: H01L21/50 ,  H01L21/561 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06582 ,  H01L2224/32145 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2224/81 ,  H01L2924/014

    Abstract: A template having tapered openings can be employed to enable injection of underfill material through gaps having a width less than a lateral dimension of an injector needle for the underfill material. Each tapered opening has a first lateral dimension on an upper side and a second lateral dimension on a lower side. Compliant material portions can be employed to accommodate variations in distance between the template and stacked semiconductor chips and/or an injector head. Optionally, another head can be employed to apply compressed gas to push out the underfill material after the underfill material is applied to the gaps. Multiple injector heads can be employed to simultaneously inject the underfill material at different sites. An adhesive layer can be substituted for the at least one lower compliant material portion.

    Abstract translation: 可以使用具有锥形开口的模板，以使得能够通过具有小于底部填充材料的注射器针的横向尺寸的间隙的间隙注入底部填充材料。 每个锥形开口具有在上侧上的第一横向尺寸和在下侧上的第二横向尺寸。 可以采用符合材料的部分来适应模板和堆叠的半导体芯片和/或注射器头之间的距离的变化。 可选地，在将底部填充材料施加到间隙之后，可以使用另一个头部来施加压缩气体以推出底部填充材料。 可以使用多个注射器头来同时将底部填充材料注入不同的位置。 粘合剂层可以代替至少一个下顺应材料部分。

    Metal oxide semiconductor (MOS)-compatible high-aspect ratio through-wafer vias and low-stress configuration thereof
    4.
    发明授权
    Metal oxide semiconductor (MOS)-compatible high-aspect ratio through-wafer vias and low-stress configuration thereof 失效
    金属氧化物半导体（MOS）兼容的高纵横比透晶片通孔及其低应力结构

    公开(公告)号：US08492901B2

    公开(公告)日：2013-07-23

    申请号：US12614062

    申请日：2009-11-06

    Applicant: Bucknell C. Webb

    Inventor： Bucknell C. Webb

    IPC: H01L23/538

    CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

    Abstract: A structure includes a wafer having a top wafer surface. The wafer defines an opening. The top wafer surface defines a first reference direction perpendicular to the top wafer surface. The wafer has a thickness in the first reference direction. The structure also includes a through-wafer via formed in the opening. The through-wafer via has a shape, when viewed in a plane perpendicular to the first reference direction and parallel to the top wafer surface, of at least one of a spiral and a C-shape. The through-wafer via has a height in the first reference direction essentially equal to the thickness of the wafer in the first reference direction. Manufacturing techniques are also disclosed.

    Abstract translation: 一种结构包括具有顶部晶片表面的晶片。 晶片限定开口。 顶部晶片表面限定垂直于顶部晶片表面的第一参考方向。 晶片具有第一基准方向的厚度。 该结构还包括形成在开口中的贯通晶片通孔。 当在垂直于第一参考方向的平面中观察并且平行于顶部晶片表面时，贯穿晶片通孔具有螺旋形和C形中的至少一种形状。 贯通晶片通孔的第一参考方向的高度基本上等于晶片在第一参考方向上的厚度。 还公开了制造技术。

    Magnetic writer having multiple gaps with more uniform magnetic fields across the gaps
    6.
    发明授权
    Magnetic writer having multiple gaps with more uniform magnetic fields across the gaps 有权
    具有多个间隙的磁记录器，跨越间隙具有更均匀的磁场

    公开(公告)号：US08385018B2

    公开(公告)日：2013-02-26

    申请号：US12611294

    申请日：2009-11-03

    Applicant: Robert G. Biskeborn ,  Philipp Herget ,  Bucknell C. Webb

    Inventor： Robert G. Biskeborn ,  Philipp Herget ,  Bucknell C. Webb

    IPC: G11B5/265

    CPC classification number: G11B5/3116 ,  G11B5/17 ,  G11B5/23 ,  G11B5/265 ,  G11B5/2652 ,  G11B5/59638

    Abstract: A magnetic device according to one embodiment includes a source of flux; a magnetic pole coupled to the source of flux, the magnetic pole having two or more gaps; and a low reluctance path positioned towards at least one of the gaps and not positioned towards at least one other of the gaps for affecting a magnetic field formed at the at least one of the gaps when the source of flux is generating flux. Other disclosed embodiments include devices having coil turns with a non-uniform placement in the magnetic yoke for altering a magnetic field formed at the at least one of the gaps during writing. In further embodiments, a geometry of the magnetic pole near or at one of the gaps is different than a geometry of the magnetic pole near or at another of the gaps to help equalize fields formed at the gaps when the source of flux is generating flux.

    Abstract translation: 根据一个实施例的磁性装置包括通量源; 耦合到磁通源的磁极，所述磁极具有两个或更多个间隙; 以及朝向所述间隙中的至少一个定位的低磁阻路径，并且朝向所述间隙中的至少另一个定位，以在所述通量源产生磁通时影响形成在所述至少一个间隙处的磁场。 其他公开的实施例包括具有在磁轭中具有不均匀布置的线圈匝的装置，用于在写入期间改变在至少一个间隙处形成的磁场。 在另外的实施例中，靠近或在其中一个间隙处的磁极的几何形状不同于磁极在靠近或另一个间隙处的几何形状，以帮助当磁通源产生磁通时在间隙处形成的场均衡。

    Metal Oxide Semiconductor (MOS)-Compatible High-Aspect Ratio Through-Wafer Vias and Low-Stress Configuration Thereof
    8.
    发明申请
    Metal Oxide Semiconductor (MOS)-Compatible High-Aspect Ratio Through-Wafer Vias and Low-Stress Configuration Thereof 失效
    金属氧化物半导体（MOS） - 兼容的高宽比通过晶片通孔和低应力配置

    公开(公告)号：US20110108958A1

    公开(公告)日：2011-05-12

    申请号：US12614062

    申请日：2009-11-06

    Applicant: Bucknell C. Webb

    Inventor： Bucknell C. Webb

    IPC: H01L23/48 ,  H01L21/3205 ,  H01L21/768

    CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

    Abstract: A structure includes a wafer having a top wafer surface. The wafer defines an opening. The top wafer surface defines a first reference direction perpendicular to the top wafer surface. The wafer has a thickness in the first reference direction. The structure also includes a through-wafer via formed in the opening. The through-wafer via has a shape, when viewed in a plane perpendicular to the first reference direction and parallel to the top wafer surface, of at least one of a spiral and a C-shape. The through-wafer via has a height in the first reference direction essentially equal to the thickness of the wafer in the first reference direction. Manufacturing techniques are also disclosed.

    Abstract translation: 一种结构包括具有顶部晶片表面的晶片。 晶片限定开口。 顶部晶片表面限定垂直于顶部晶片表面的第一参考方向。 晶片具有第一基准方向的厚度。 该结构还包括形成在开口中的贯通晶片通孔。 当在垂直于第一参考方向的平面中观察并且平行于顶部晶片表面时，贯穿晶片通孔具有螺旋形和C形中的至少一种形状。 贯通晶片通孔的第一参考方向的高度基本上等于晶片在第一参考方向上的厚度。 还公开了制造技术。

    Cooling structure using rigid movable elements
    9.
    发明授权
    Cooling structure using rigid movable elements 有权
    使用刚性可移动元件的冷却结构

    公开(公告)号：US07362582B2

    公开(公告)日：2008-04-22

    申请号：US11151905

    申请日：2005-06-14

    Applicant: John P. Karidis ,  Mark D. Schultz ,  Bucknell C. Webb

    Inventor： John P. Karidis ,  Mark D. Schultz ,  Bucknell C. Webb

    IPC: H05K7/20

    CPC classification number: H01L23/433 ,  H01L23/427 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A structure for cooling an electronic device is disclosed. The structure includes a compressible top layer disposed over the electronic device. The structure further includes a plurality of rigid elements disposed between the top layer and the electronic device for providing a heat path from the electronic device and wherein the plurality of rigid elements provide mechanical compliance. In another alternative, the structure further includes a conformable heat-conducting layer disposed over the electronic device, wherein a bottom end of the plurality of rigid elements is coupled to the conformable heat-conducting layer.

    Abstract translation: 公开了一种用于冷却电子设备的结构。 该结构包括设置在电子设备上的可压缩顶层。 该结构还包括设置在顶层和电子设备之间的多个刚性元件，用于提供来自电子设备的热路径，并且其中多个刚性元件提供机械顺应性。 在另一替代方案中，结构还包括设置在电子设备上的适形导热层，其中多个刚性元件的底端联接到适形导热层。

    Self-servo-writing multi-slot timing pattern
    10.
    发明授权
    Self-servo-writing multi-slot timing pattern 失效
    自伺服写多槽定时模式

    公开(公告)号：US07268963B2

    公开(公告)日：2007-09-11

    申请号：US10903153

    申请日：2004-07-30

    Applicant: Timothy J. Chainer ,  Mark D. Schultz ,  Bucknell C. Webb

    Inventor： Timothy J. Chainer ,  Mark D. Schultz ,  Bucknell C. Webb

    IPC: G11B5/09 ,  G11B21/02 ,  G11B5/596

    CPC classification number: G11B5/59633 ,  G11B5/59605

    Abstract: Self-servo-writing of multi-slot timing patterns is described. Individual timing marks are replaced with groups of timing mark slots. At each timing mark location, a time measurement is made by detecting a timing mark in one of the slots. Also, extensions to the existing timing marks are written in other slots. The combination of timing measurements at every timing mark and extensions to those timing marks written at every opportunity improves the overall precision of the timing propagation. The improved accuracy of timing mark placement produces a commensurate improvement in the placement of the concomitantly written servo-data. In addition, the alignment accuracy of the written pattern is less sensitive to variations in rotation speed and variations in the shape of written transitions. Moreover, only a single disk revolution is required at each servo radius to write servo data and propagate the timing marks to maintain timing alignment.

    Abstract translation: 描述了多时隙定时模式的自伺服写入。 单个定时标记被定时标记位置组替换。 在每个定时标记位置，通过检测其中一个时隙中的定时标记来进行时间测量。 此外，现有时序标记的扩展也写在其他插槽中。 每个定时标记的定时测量和在每个机会上写入的定时标记的扩展的组合可以提高定时传播的总体精度。 定时标记放置的改进精度在同时写入的伺服数据的位置上产生相应的改进。 此外，写入的图案的对准精度对旋转速度的变化和写入的转变的形状的变化较不敏感。 此外，在每个伺服半径处仅需要一次盘旋转以写入伺服数据并传播定时标记以保持定时对准。

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