公开(公告)号：US5851307A

公开(公告)日：1998-12-22

申请号：US842092

申请日：1997-04-28

申请人： Mark C. Gilmer ,  Mark I. Gardner ,  Robert Paiz

发明人： Mark C. Gilmer ,  Mark I. Gardner ,  Robert Paiz

IPC分类号： B08B3/08 ,  B08B9/00 ,  C23C16/44

CPC分类号： C23C16/4407 ,  B08B3/08 ,  B08B9/00 ,  Y10S438/905

摘要： A method for in-situ cleaning of polysilicon-coated quartz furnaces are presented. Traditionally, disassembling and reassembling the furnace is required to clean the quartz. This procedure requires approximately four days of down time which can be very costly for a company. In addition, cleaning the quartz requires large baths filled with a cleaning agent. These baths occupy a large amount of laboratory space and require a large amount of the cleaning agent. Cleaning the furnace in-situ eliminates the very time consuming procedure of assembling and disassembling the furnace and at the same time requires less laboratory space and less amount of cleaning agent. The polysilicon remover may be either a mixture of hydrofluoric and nitric acid or TMAH. TMAH is preferred because it less hazardous than hydrofluoric acid and compatible with more materials. The cleaning agent may be introduced into the furnace either from the built-in injectors or from additionally installed injectors. If the built-in injectors are used, the input system of the furnace is cleaned in addition to the quartz inner lining.

摘要翻译： 提出了一种用于原位清洗多晶硅涂覆的石英炉的方法。 传统上，需要拆卸和重新组装炉子来清洁石英。 该程序需要大约四天的停机时间，这对公司来说可能是非常昂贵的。 此外，清洁石英需要大量的填充有清洁剂的浴池。 这些浴室占据大量的实验室空间，需要大量的清洁剂。 原地清洗炉子消除了组装和拆卸炉子非常耗时的过程，同时需要更少的实验室空间和更少量的清洁剂。 多晶硅去除剂可以是氢氟酸和硝酸或TMAH的混合物。 TMAH是优选的，因为它比氢氟酸更危险，并且与更多的材料相容。 清洁剂可以从内置注射器或另外安装的注射器引入炉中。 如果使用内置注射器，除了石英内衬之外，还要清洁炉子的输入系统。

公开(公告)号：US5849643A

公开(公告)日：1998-12-15

申请号：US862516

申请日：1997-05-23

申请人： Mark C. Gilmer ,  Mark I. Gardner ,  Daniel Kadosh

发明人： Mark C. Gilmer ,  Mark I. Gardner ,  Daniel Kadosh

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L21/306

CPC分类号： H01L21/28185 ,  H01L21/28211 ,  H01L29/51 ,  Y10S438/905 ,  Y10S438/906

摘要： A method of growing an oxide film in which the upper surface of a semiconductor substrate is cleaned and the semiconductor substrate is dipped into an acidic solution to remove any native oxide from the upper surface. The substrate is then directly transferred from the acidic solution to an oxidation chamber. The oxidation chamber initially contains an inert ambient maintained at a temperature of less than approximately 500.degree. C. The transfer is accomplished without substantially exposing the substrate to oxygen thereby preventing the formation of a native oxide film on the upper surface of the substrate. Thereafter, a fluorine terminated upper surface is formed on the semiconductor substrate. The temperature within the chamber is then ramped from the first temperature to a second or oxidizing temperature if approximately 700.degree. C. to 850.degree. C. The presence of the fluorine terminated upper surface substantially prevents oxidation of the semiconductor substrate during the temperature ramp. A silicon-oxide film such as silicon dioxide is then grown on the fluorine terminated upper surface of the semiconductor substrate by introducing an oxidizing ambient into the chamber. After the formation or growth of the silicon-oxide, polysilicon is deposited on the silicon oxide film.

摘要翻译： 一种生长氧化膜的方法，其中清洁半导体衬底的上表面并将半导体衬底浸入酸性溶液中以从上表面去除任何天然氧化物。 然后将基底从酸性溶液直接转移到氧化室。 氧化室最初包含保持在小于约500℃的温度的惰性环境。转移完成而基本上不暴露于氧气，从而防止在衬底的上表面上形成自然氧化膜。 此后，在半导体衬底上形成氟端接的上表面。 如果约700℃至850℃，则室内的温度然后从第一温度升高至第二温度或氧化温度。氟端接的上表面的存在基本上防止了温度斜坡期间半导体衬底的氧化。 然后通过将氧化环境引入室中，在半导体衬底的氟封端的上表面上生长二氧化硅等氧化硅膜。 在氧化硅的形成或生长之后，多晶硅沉积在氧化硅膜上。

公开(公告)号：US5840610A

公开(公告)日：1998-11-24

申请号：US784741

申请日：1997-01-16

申请人： Mark C. Gilmer ,  Mark I. Gardner

发明人： Mark C. Gilmer ,  Mark I. Gardner

IPC分类号： H01L21/28 ,  H01L21/314 ,  H01L29/51 ,  H01L21/336 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L21/3145 ,  H01L29/518

摘要： A semiconductor manufacturing process in which single crystal silicon substrate is immersed into an oxidation chamber maintained at a first temperature between 400.degree. and 700.degree. C. for a first duration. The oxidation chamber includes a first ambient gas of N.sub.2 or Argon. A second ambient gas is then introduced into the oxidation chamber. The second ambient gas includes a fluorine species to remove any residual oxide from the upper surface of the semiconductor substrate and to form a fluorine terminated upper surface. The ambient temperature within said oxidation chamber is then ramped to a second temperature in the range of approximately 600.degree. to 950.degree. C. A third ambient gas is introduced into said oxidation chamber to form a base oxide layer on the fluorine terminated upper surface of said semiconductor substrate. The third ambient gas includes oxygen and, preferably, the base oxide layer consists essentially of silicon and oxide. A fourth ambient gas, which includes a nitrogen species, is then introduced into the oxidation chamber and the base oxide layer is reoxidized to form an oxynitride layer. Thereafter, a conductive gate structure is formed on the oxynitride layer and a source/drain impurity distribution is introduced into a pair of source/drain regions within the semiconductor substrate.

摘要翻译： 一种半导体制造工艺，其中将单晶硅衬底浸入保持在400℃和700℃之间的第一温度的氧化室中持续第一时间。 氧化室包括N2或氩气的第一环境气体。 然后将第二环境气体引入氧化室。 第二环境气体包括氟物质，以从半导体衬底的上表面去除任何残余的氧化物并形成氟端接的上表面。 然后将所述氧化室内的环境温度升温至约600℃至950℃的第二温度。将第三环境气体引入所述氧化室中，以在所述氧化室的氟端接的上表面上形成氧化基底层 半导体衬底。 第三环境气体包括氧，并且优选地，氧化物层基本上由硅和氧化物组成。 然后将包括氮物质的第四环境气体引入到氧化室中，并且氧化底层氧化层以形成氧氮化物层。 此后，在氧氮化物层上形成导电栅极结构，并且将源极/漏极杂质分布引入到半导体衬底内的一对源极/漏极区域中。

公开(公告)号：US5821172A

公开(公告)日：1998-10-13

申请号：US779264

申请日：1997-01-06

申请人： Mark C. Gilmer ,  Mark I. Gardner

发明人： Mark C. Gilmer ,  Mark I. Gardner

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L21/322

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L29/518

摘要： A semiconductor manufacturing process in which a single crystal silicon semiconductor substrate is immersed in an oxidation chamber maintained at a first temperature preferably between 400.degree. and 700.degree. C. for a first duration. During the first duration, the oxidation chamber comprises a first ambient gas of N.sub.2 or Argon. Thereafter, the ambient temperature within the oxidation chamber is ramped to a second temperature in the range of approximately 600.degree. to 1100.degree. C. NH.sub.3 is then introduced into the oxidation chamber simultaneously with either NO or N.sub.2 O to form an oxynitride layer. Thereafter, a conductive gate structure is formed on the oxynitride layer and a source/drain impurity distribution is introduced into a pair of source/drain regions laterally displaced on either side of the channel region of the semiconductor substrate. The channel region is aligned with the conductive gate. Preferably, the resistivity of an epitaxial layer of the semiconductor substrate is in the range of approximately 10 to 15 .OMEGA.-cm. In one embodiment, the first ambient gas further includes 1 to 10% oxygen and the first temperature is in the range of approximately 600.degree. C. to 700.degree. C. In one embodiment, a thin base oxide film consisting essentially of silicon an oxygen is formed on the upper surface of the semiconductor substrate prior to the oxynitride formation. In one embodiment of the invention, the oxynitride layer is annealed in an N.sub.2 ambient at an anneal temperature in the range of approximately 600.degree. C. to 1100.degree. C. for a duration in the range of 30 seconds to 20 minutes.

摘要翻译： 一种半导体制造工艺，其中将单晶硅半导体衬底浸入保持在第一温度的氧化室中，优选在400至700℃之间，持续第一时间。 在第一持续时间期间，氧化室包括N2或氩气的第一环境气体。 此后，氧化室内的环境温度升至约600℃至1100℃范围内的第二温度。然后将NH 3与NO或N 2 O同时导入氧化室以形成氧氮化物层。 此后，在氧氮化物层上形成导电栅极结构，并且将源极/漏极杂质分布引入在半导体衬底的沟道区的任一侧上横向移位的一对源/漏区中。 沟道区域与导电栅极对准。 优选地，半导体衬底的外延层的电阻率在约10至15欧姆 - 厘米的范围内。 在一个实施方案中，第一环境气体还包括1至10％的氧，第一温度在约600℃至700℃的范围内。在一个实施方案中，基本上由硅组成氧的氧化薄膜 在氧氮化物形成之前形成在半导体衬底的上表面上。 在本发明的一个实施方案中，氧氮化物层在N 2环境中在约600℃至1100℃的退火温度下退火持续30秒至20分钟的范围。

公开(公告)号：US06265749B1

公开(公告)日：2001-07-24

申请号：US08950042

申请日：1997-10-14

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L2976

CPC分类号： H01L21/28202 ,  H01L21/28097 ,  H01L21/28194 ,  H01L29/4975 ,  H01L29/518 ,  H01L29/6659

摘要： A transistor is provided having a metal silicide gate spaced above a semiconductor substrate by a high-dielectric-constant ceramic gate dielectric. The entire gate conductor is preferably composed of a metal silicide. In an embodiment, the metal silicide is cobalt silicide and the ceramic gate dielectric is barium strontium titanate, lead lanthanum zirconate titanate barium zirconate titanate, cerium oxide, or tin oxide. In another embodiment, the ceramic gate dielectric has nitrogen atoms incorporated therein. The transistor may also include dielectric spacers adjacent opposed sidewall surfaces of the gate conductor, lightly doped drain regions arranged underneath the spacers, and source and drain regions arranged adjacent the lightly doped drain regions.

摘要翻译： 提供晶体管，其具有通过高介电常数陶瓷栅极电介质在半导体衬底上间隔开的金属硅化物栅极。 整个栅极导体优选由金属硅化物构成。 在一个实施例中，金属硅化物是硅化钴，陶瓷栅极电介质是钛酸锶钡，锆钛酸铅镧锆钛酸钡，氧化铈或氧化锡。 在另一个实施例中，陶瓷栅极电介质具有并入其中的氮原子。 晶体管还可以包括邻近栅极导体的相对侧壁表面的介电间隔物，布置在间隔物下面的轻掺杂漏极区域和邻近轻掺杂漏极区域排列的源极和漏极区域。

公开(公告)号：US06214690B1

公开(公告)日：2001-04-10

申请号：US08993415

申请日：1997-12-18

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L2176

CPC分类号： H01L21/762 ,  H01L21/76224

摘要： The present invention generally provides a semiconductor device and fabrication process in which gate electrode formation is integrated with the formation of isolation regions. Consistent with one embodiment of the invention, the semiconductor device is formed by forming at least two adjacent gate electrode stacks of the substrate. A layer of dielectric material is formed over regions of the substrate between the two adjacent gate electrode stacks and portions of the dielectric material layer are selectively removed to leave an isolation block of the dielectric material between the two adjacent gate electrode stacks. The gate electrode stacks may, for example, have a thickness ranging from about 2,500 to 6,000 Å. In accordance with one aspect of the invention, active regions are formed in the substrate between the isolation block and at least one of the gate electrode stacks.

摘要翻译： 本发明通常提供半导体器件和制造工艺，其中栅电极形成与形成隔离区域一体化。 根据本发明的一个实施例，半导体器件通过形成至少两个相邻的栅极电极堆叠形成。 在两个相邻的栅电极堆叠之间的衬底的区域上形成介电材料层，并且选择性地去除介电材料层的部分，以在两个相邻的栅极电极堆叠之间留下介电材料的隔离块。 栅极电极堆叠例如可以具有从约2,500至6,000埃的厚度。 根据本发明的一个方面，在隔离块和至少一个栅电极堆叠之间的衬底中形成有源区。

公开(公告)号：US06214123B1

公开(公告)日：2001-04-10

申请号：US09137902

申请日：1998-08-20

申请人： Mark I. Gardner ,  Mark C. Gilmer ,  Robert Paiz

发明人： Mark I. Gardner ,  Mark C. Gilmer ,  Robert Paiz

IPC分类号： C23C1600

CPC分类号： C23C16/45514 ,  C23C16/4409 ,  C23C16/4584

摘要： The present disclosure relates to a chemical vapor deposition system including a chemical vapor deposition chamber, and a circlet wafer positioned within the chemical vapor deposition chamber. The circlet wafer is mounted on a rotatable member that at least partially extends through an opening of the wafer. A drive mechanism is used to rotate the rotatable member and the circlet wafer. The system also includes a gas injector for injecting reactive gases toward the circlet wafer. The present disclosure also relates to a chemical vapor deposition system including a chemical vapor deposition chamber, a wafer positioned within the chemical vapor deposition chamber, and a gas injector for injecting first and second reactive gases toward the wafer. The gas injector includes a mixing region for mixing the first and second reactive gases before the first and second reactive gases are discharged from the gas injector.

摘要翻译： 本公开涉及包括化学气相沉积室和位于化学气相沉积室内的圆盘晶片的化学气相沉积系统。 小圆片安装在至少部分地延伸穿过晶片的开口的可旋转构件上。 使用驱动机构来旋转可旋转构件和小圆片。 该系统还包括用于将反应性气体注入到小圆片的气体注射器。 本公开还涉及包括化学气相沉积室，位于化学气相沉积室内的晶片的化学气相沉积系统和用于向晶片注入第一和第二反应气体的气体注入器。 气体喷射器包括用于在第一和第二反应气体从气体喷射器排出之前混合第一和第二反应气体的混合区域。

公开(公告)号：US06197647B1

公开(公告)日：2001-03-06

申请号：US09198195

申请日：1998-11-23

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21336

CPC分类号： H01L21/28202 ,  H01L21/28035 ,  H01L21/28211 ,  H01L29/42364 ,  H01L29/518

摘要： A semiconductor process in which a low temperature oxidation of a semiconductor substrate upper surface followed by an in situ deposition of polysilicon are used to create a thin oxide MOS structure. Preliminarily, the upper surface of a semiconductor substrate is cleaned, preferably with a standard RCA clean procedure. A gate dielectric layer is then formed on the upper surface of the substrate. A first polysilicon layer is then in situ deposited on the gate dielectric layer. An upper portion of the first polysilicon layer is then oxidized and the oxidized portion is thereafter removed from the upper surface of the first polysilicon layer. A second polysilicon layer is subsequently deposited upon the first polysilicon layer. Preferably, the formation of the gate dielectric on the semiconductor substrate upper surface comprises annealing the semiconductor substrate in an ambient comprising an inert species and O2. The ambient temperature of the first oxidation chamber is preferably maintained at a temperature less than approximately 300° C. during the formation of the gate dielectric. The first polysilicon layer, in the preferred embodiment, is deposited in situ such that the semiconductor substrate remains within the first oxidation chamber during the deposition of the first polysilicon layer. The oxidation of an upper portion of the first polysilicon layer is preferably accomplished in a nitrogen bearing ambient so that nitrogen is introduced into the first polysilicon layer to inhibit the penetration of mobile impurities across the gate dielectric into the channel region of the transistor and enhance the device properties.

摘要翻译： 利用半导体工艺，其中半导体衬底上表面的低温氧化接着原位沉积多晶硅以产生薄氧化物MOS结构。 最初，半导体衬底的上表面最好用标准的RCA清洁程序进行清洁。 然后在衬底的上表面上形成栅介质层。 然后将第一多晶硅层原位沉积在栅极介电层上。 然后将第一多晶硅层的上部氧化，然后从第一多晶硅层的上表面除去氧化部分。 随后在第一多晶硅层上沉积第二多晶硅层。 优选地，半导体衬底上表面上的栅极电介质的形成包括在包含惰性物质和O 2的环境中退火半导体衬底。 在形成栅极电介质期间，第一氧化室的环境温度优选保持在小于约300℃的温度。 在优选实施例中，第一多晶硅层原位沉积，使得半导体衬底在沉积第一多晶硅层期间保持在第一氧化室内。 第一多晶硅层的上部的氧化优选在含氮环境中进行，以便将氮引入到第一多晶硅层中，以阻止移动杂质穿过栅极电介质渗入晶体管的沟道区域并增强 设备属性。

公开(公告)号：US06197644B1

公开(公告)日：2001-03-06

申请号：US09187258

申请日：1998-11-06

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21336

CPC分类号： H01L21/823425

摘要： In an integrated circuit, a pair of IGFET devices can be formed with reduced dimensions without requiring the use of higher resolution optical masks. A gate electrode is formed with a layer of silicon nitride and a photoresist layer formed thereon. The dimensions of the photoresist layer are reduced by a trim etch and the dimension of the nitride layer reduced by a nitride etch. After removing the photoresist layer, a silicon oxide layer is grown over the exposed gate electrode and substrate. The nitride layer is removed leaving a pattern in the silicon oxide layer. An anisotropic etch guided by the pattern in the silicon oxide layer divides the gate electrode into two portions with an aperture therebetween. By proper doping, a IGFET structure can be formed that has two IGFET devices having a shared source/drain region and occupying the same area on the surface of the substrate as a single IGFET device previously occupied.

摘要翻译： 在集成电路中，可以以较小的尺寸形成一对IGFET器件，而不需要使用更高分辨率的光掩模。 栅电极形成有氮化硅层和形成在其上的光致抗蚀剂层。 通过修整蚀刻来减小光致抗蚀剂层的尺寸，并且通过氮化物蚀刻减少氮化物层的尺寸。 在除去光致抗蚀剂层之后，在暴露的栅电极和衬底上生长氧化硅层。 去除氮化物层，留下氧化硅层中的图案。 由氧化硅层中的图案引导的各向异性蚀刻将栅电极分成两部分，其间具有孔。 通过适当的掺杂，可以形成IGFET结构，其具有两个具有共享源极/漏极区域的IGFET器件，并且与先前占据的单个IGFET器件在衬底的表面上占据相同的面积。

公开(公告)号：US06172402B2

公开(公告)日：2001-01-09

申请号：US09090466

申请日：1998-06-04

申请人： Mark I. Gardner ,  Mark C. Gilmer ,  Daniel Kadosh

发明人： Mark I. Gardner ,  Mark C. Gilmer ,  Daniel Kadosh

IPC分类号： H01L2701

CPC分类号： H01L21/76237 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0921

摘要： An integrated circuit includes a plurality of transistors formed to include insulative punchthrough regions. Each of the plurality of transistors includes a channel formed upon a substrate, an insulative punchthrough region formed below the channel, a source formed upon the insulative punchthrough region residing adjacent a first end of the channel, a drain formed upon the insulative punchthrough region residing adjacent a second end of the channel, a gate oxide formed above the channel and a gate conductor formed above the gate oxide. Isolation regions may also be formed in the substrate that have an etch stop defination that was formed upon formation of the insulative punchthrough region. A voltage threshold region may be formed between the gate oxide and the channel and lightly doped regions may be formed adjacent the channel. The insulative punchthrough region may be and oxide layer formed within the substrate in an oxygen implant step that also formed the etch stop defination. The transistors and other circuit elements formed in the substrate may be interconnected to form an integrated circuit.

摘要翻译： 集成电路包括形成为包括绝缘穿透区域的多个晶体管。 多个晶体管中的每一个包括形成在基板上的沟道，形成在沟道下方的绝缘穿透区域，形成在与沟道的第一端相邻的绝缘穿透区域上的源极，形成在绝缘穿透区域上的漏极， 沟道的第二端，形成在沟道上方的栅极氧化物和形成在栅极氧化物上方的栅极导体。 绝缘区域也可以形成在衬底中，其具有在形成绝缘穿通区域时形成的蚀刻停止定义。 可以在栅极氧化物和沟道之间形成电压阈值区域，并且可以在沟道附近形成轻掺杂区域。 绝缘穿透区域可以是氧化层，也可以形成在氧化物注入步骤中的衬底内，并形成蚀刻停止。 形成在衬底中的晶体管和其它电路元件可以互连以形成集成电路。