公开(公告)号：US5849643A

公开(公告)日：1998-12-15

申请号：US862516

申请日：1997-05-23

申请人： Mark C. Gilmer ,  Mark I. Gardner ,  Daniel Kadosh

发明人： Mark C. Gilmer ,  Mark I. Gardner ,  Daniel Kadosh

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L21/306

CPC分类号： H01L21/28185 ,  H01L21/28211 ,  H01L29/51 ,  Y10S438/905 ,  Y10S438/906

摘要： A method of growing an oxide film in which the upper surface of a semiconductor substrate is cleaned and the semiconductor substrate is dipped into an acidic solution to remove any native oxide from the upper surface. The substrate is then directly transferred from the acidic solution to an oxidation chamber. The oxidation chamber initially contains an inert ambient maintained at a temperature of less than approximately 500.degree. C. The transfer is accomplished without substantially exposing the substrate to oxygen thereby preventing the formation of a native oxide film on the upper surface of the substrate. Thereafter, a fluorine terminated upper surface is formed on the semiconductor substrate. The temperature within the chamber is then ramped from the first temperature to a second or oxidizing temperature if approximately 700.degree. C. to 850.degree. C. The presence of the fluorine terminated upper surface substantially prevents oxidation of the semiconductor substrate during the temperature ramp. A silicon-oxide film such as silicon dioxide is then grown on the fluorine terminated upper surface of the semiconductor substrate by introducing an oxidizing ambient into the chamber. After the formation or growth of the silicon-oxide, polysilicon is deposited on the silicon oxide film.

摘要翻译： 一种生长氧化膜的方法，其中清洁半导体衬底的上表面并将半导体衬底浸入酸性溶液中以从上表面去除任何天然氧化物。 然后将基底从酸性溶液直接转移到氧化室。 氧化室最初包含保持在小于约500℃的温度的惰性环境。转移完成而基本上不暴露于氧气，从而防止在衬底的上表面上形成自然氧化膜。 此后，在半导体衬底上形成氟端接的上表面。 如果约700℃至850℃，则室内的温度然后从第一温度升高至第二温度或氧化温度。氟端接的上表面的存在基本上防止了温度斜坡期间半导体衬底的氧化。 然后通过将氧化环境引入室中，在半导体衬底的氟封端的上表面上生长二氧化硅等氧化硅膜。 在氧化硅的形成或生长之后，多晶硅沉积在氧化硅膜上。

公开(公告)号：US06172402B2

公开(公告)日：2001-01-09

申请号：US09090466

申请日：1998-06-04

申请人： Mark I. Gardner ,  Mark C. Gilmer ,  Daniel Kadosh

发明人： Mark I. Gardner ,  Mark C. Gilmer ,  Daniel Kadosh

IPC分类号： H01L2701

CPC分类号： H01L21/76237 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0921

摘要： An integrated circuit includes a plurality of transistors formed to include insulative punchthrough regions. Each of the plurality of transistors includes a channel formed upon a substrate, an insulative punchthrough region formed below the channel, a source formed upon the insulative punchthrough region residing adjacent a first end of the channel, a drain formed upon the insulative punchthrough region residing adjacent a second end of the channel, a gate oxide formed above the channel and a gate conductor formed above the gate oxide. Isolation regions may also be formed in the substrate that have an etch stop defination that was formed upon formation of the insulative punchthrough region. A voltage threshold region may be formed between the gate oxide and the channel and lightly doped regions may be formed adjacent the channel. The insulative punchthrough region may be and oxide layer formed within the substrate in an oxygen implant step that also formed the etch stop defination. The transistors and other circuit elements formed in the substrate may be interconnected to form an integrated circuit.

摘要翻译： 集成电路包括形成为包括绝缘穿透区域的多个晶体管。 多个晶体管中的每一个包括形成在基板上的沟道，形成在沟道下方的绝缘穿透区域，形成在与沟道的第一端相邻的绝缘穿透区域上的源极，形成在绝缘穿透区域上的漏极， 沟道的第二端，形成在沟道上方的栅极氧化物和形成在栅极氧化物上方的栅极导体。 绝缘区域也可以形成在衬底中，其具有在形成绝缘穿通区域时形成的蚀刻停止定义。 可以在栅极氧化物和沟道之间形成电压阈值区域，并且可以在沟道附近形成轻掺杂区域。 绝缘穿透区域可以是氧化层，也可以形成在氧化物注入步骤中的衬底内，并形成蚀刻停止。 形成在衬底中的晶体管和其它电路元件可以互连以形成集成电路。

公开(公告)号：US06232637B1

公开(公告)日：2001-05-15

申请号：US09249954

申请日：1999-02-12

申请人： Mark I. Gardner ,  Daniel Kadosh

发明人： Mark I. Gardner ,  Daniel Kadosh

IPC分类号： H01L31036

CPC分类号： H01L27/0688 ,  H01L21/8221

摘要： An integrated circuit fabrication process is provided in which an elevated doped polysilicon structure may be formed. The elevated structure may serve as a junction area of a transistor formed entirely within and upon the elevated polysilicon. The elevated structure frees up space within the lower level substrate for additional transistors and/or lateral interconnect, a benefit of which is to promote higher packing density within the integrated circuit. A transistor is provided which includes a gate conductor spaced between a pair of junctions. A primary interlevel dielectric is deposited across the transistor. A polysilicon structure is formed within a select portion of the upper surface of the primary interlevel dielectric. The polysilicon structure is a spaced distance above and a lateral distance from the transistor. A dopant is implanted into the polysilicon structure. A secondary interlevel dielectric is deposited across the primary interlevel dielectric and the doped polysilicon structure. Select portions of the primary and secondary interlevel dielectrics are then removed to expose one of the junctions and a portion of the doped polysilicon structure arranged proximate this junction. An interconnect is formed contiguously between the junction and the polysilicon structure by depositing a conductive material within the removed portions.

摘要翻译： 提供了一种集成电路制造工艺，其中可以形成高掺杂多晶硅结构。 升高的结构可以用作完全在升高的多晶硅内部和之上形成的晶体管的结区域。 升高的结构释放了用于附加晶体管和/或横向互连的下层衬底内的空间，其益处是促进集成电路内的更高的堆积密度。 提供晶体管，其包括在一对结之间间隔开的栅极导体。 在晶体管两端沉积初级层间电介质。 在初级层间电介质的上表面的选择部分内形成多晶硅结构。 多晶硅结构是距离晶体管的上方和横向距离之间的间隔距离。 将掺杂剂注入到多晶硅结构中。 次级层间电介质沉积在初级层间电介质和掺杂多晶硅结构之间。 选择部分初级和次级层间电介质然后被去除以暴露出一个结点，并且掺杂多晶硅结构的一部分布置在该结附近。 通过在去除的部分内沉积导电材料，在结和多晶硅结构之间连续地形成互连。

公开(公告)号：US06218251B1

公开(公告)日：2001-04-17

申请号：US09187894

申请日：1998-11-06

申请人： Daniel Kadosh ,  Mark I. Gardner

发明人： Daniel Kadosh ,  Mark I. Gardner

IPC分类号： H01L21336

CPC分类号： H01L29/66598 ,  H01L29/6653 ,  H01L29/66659 ,  H01L29/7835

摘要： In an IGFET device having at least one source/drain region with a lightly-doped sub-region proximate a channel region, the source/drain regions are formed by first implanting ions with parameters to form lightly-doped source/drain regions. A high density plasma deposition provides at least one spacer having preselected characteristics. As a result of the spacer characteristics, an ion implantation with parameters to form normally-doped source/drain regions is shadowed by the spacer. A portion of the source/drain region shadowed by the spacer results in a lightly-doped source/drain sub-region proximate the channel region. According to a second embodiment of the invention, the ion implantation resulting in the lightly-doped source/drain regions is eliminated. Instead, the spacer(s) formed by the high density plasma deposition and subsequent etching process only partially shadows the ion implantation that would otherwise result in normal doping of the source/drain regions. The parameters of the spacer(s) resulting from the high density plasma deposition and subsequent etching process result in a lightly-doped source/drain sub-region proximate the channel region. The shadowing of the spacer decreases with distance from the gate structure and results in a normal doping level for the portion of the source/drain terminal not shadowed by the spacer.

摘要翻译： 在具有至少一个具有靠近沟道区的轻掺杂子区域的源极/漏极区域的IGFET器件中，通过首先用参数注入离子以形成轻掺杂的源极/漏极区域来形成源极/漏极区域。 高密度等离子体沉积提供至少一个具有预选特性的间隔物。 作为间隔物特性的结果，具有形成常态掺杂源极/漏极区域的参数的离子注入被间隔物遮蔽。 由间隔物遮蔽的源极/漏极区域的一部分导致靠近沟道区域的轻掺杂源极/漏极子区域。 根据本发明的第二实施例，消除了导致轻掺杂源/漏区的离子注入。 替代地，通过高密度等离子体沉积和随后的蚀刻工艺形成的间隔物仅部分地影响否则将导致源/漏区的正常掺杂的离子注入。 由高密度等离子体沉积和随后的蚀刻工艺产生的间隔物的参数导致靠近沟道区的轻掺杂的源极/漏极子区域。 间隔物的阴影随着与栅极结构的距离而减小，并且导致源极/漏极端子的未被间隔物遮蔽的部分的正常掺杂水平。

公开(公告)号：US06172381B2

公开(公告)日：2001-01-09

申请号：US09219146

申请日：1998-12-22

申请人： Mark I. Gardner ,  Daniel Kadosh

发明人： Mark I. Gardner ,  Daniel Kadosh

IPC分类号： H01L2702

CPC分类号： H01L21/76897 ,  H01L21/76838 ,  H01L21/8221 ,  H01L23/5226 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit fabrication process is provided in which an elevated doped polysilicon structure may be formed and isolated from another polysilicon structure lying in the same elevated plane. The elevated structure may serve as a junction area of a transistor formed entirely within and upon the elevated polysilicon. The elevated structure frees up space within the lower level substrate for additional transistors and/or lateral interconnect, a benefit of which is to promote higher packing density within the integrated circuit. A first transistor is provided which is disposed upon and within a silicon-based substrate. A primary interlevel dielectric is deposited across the transistor and the substrate. Polysilicon may then be deposited across the primary interlevel dielectric and doped using ion implantation. A second transistor may be formed upon and within a portion of the polysilicon layer. The second transistor has a pair of implant regions spaced from each other by a gate conductor and a pair of oxide spacers arranged on opposed sidewall surfaces of the gate conductor. Part of the polysilicon layer is removed such that polysilicon only extends under the gate conductor and terminates a pre-defined distance from each of the pair of oxide spacers. A pair of junctions remain for the second transistor that are defined between an etched lateral edge and an oxide spacer. A second interlevel dielectric may be deposited across the second transistor and exposed areas of the primary interlevel dielectric to isolate the transistor from other active devices.

摘要翻译： 提供了一种集成电路制造工艺，其中可以形成高掺杂多晶硅结构并将其与位于同一高架平面中的另一多晶硅结构隔离。 升高的结构可以用作完全在升高的多晶硅内部和之上形成的晶体管的结区域。 升高的结构释放了用于附加晶体管和/或横向互连的下层衬底内的空间，其益处是促进集成电路内的更高的堆积密度。 提供了第一晶体管，其设置在硅基衬底上并且位于硅基衬底内。 在晶体管和衬底两端沉积初级层间电介质。 然后可以将多晶硅沉积在初级层间电介质上并使用离子注入进行掺杂。 可以在多晶硅层的一部分上形成第二晶体管。 第二晶体管具有通过栅极导体和布置在栅极导体的相对的侧壁表面上的一对氧化物隔离物彼此隔开的一对注入区域。 去除多晶硅层的一部分，使得多晶硅仅在栅极导体下方延伸并且终止与一对氧化物间隔物中的每一个的预定距离。 在蚀刻的侧边缘和氧化物间隔物之间​​限定的第二晶体管保留一对结。 可以跨越第二晶体管和初级层间电介质的暴露区域沉积第二层间电介质以将晶体管与其它有源器件隔离。

公开(公告)号：US06104069A

公开(公告)日：2000-08-15

申请号：US187462

申请日：1998-11-04

申请人： Michael Duane ,  Daniel Kadosh ,  Mark I. Gardner

发明人： Michael Duane ,  Daniel Kadosh ,  Mark I. Gardner

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L21/768 ,  H01L29/417 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/66568 ,  H01L21/76877 ,  H01L29/41725 ,  H01L29/41733 ,  H01L29/66575 ,  H01L29/7833 ,  H01L21/2257 ,  H01L29/665 ,  Y10S257/90

摘要： A process for forming a semiconductor device having an elevated active region is disclosed. The process includes forming a plurality of gate electrodes on the semiconductor substrate and disposing a thick oxide layer over the gate electrodes. A trench is formed in a thick oxide layer and is filled with a polysilicon material. The polysilicon material is subsequently doped in order to form an elevated active region above an active region of the substrate.

摘要翻译： 公开了一种用于形成具有升高的有源区的半导体器件的工艺。 该工艺包括在半导体衬底上形成多个栅电极，并在栅电极上设置厚氧化层。 在厚的氧化物层中形成沟槽并填充有多晶硅材料。 随后掺杂多晶硅材料以便在衬底的有源区上方形成升高的有源区。

公开(公告)号：US6097096A

公开(公告)日：2000-08-01

申请号：US890377

申请日：1997-07-11

申请人： Mark I. Gardner ,  Fred Hause ,  Daniel Kadosh

发明人： Mark I. Gardner ,  Fred Hause ,  Daniel Kadosh

IPC分类号： H01L21/768 ,  H01L21/98 ,  H01L23/532 ,  H01L25/065 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L25/50 ,  H01L21/76801 ,  H01L21/76834 ,  H01L23/5329 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/05571 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/3011

摘要： A high density integrated circuit structure and method of making the same includes providing a first silicon substrate structure having semiconductor device formations in accordance with a first circuit implementation and metal interlevel lines disposed on a top surface thereof and a second silicon substrate structure having a second circuit implementation and metal interlevel lines disposed on a top surface thereof. The first substrate structure includes a planarized low-K dielectric disposed between the metal interlevel lines and a protective coating separating the metal interlevel lines from the low-K dielectric, the metal interlevel lines of the first silicon substrate structure have a melting temperature on the order of less than 500.degree. C. and the low-K dielectric having a dielectric K-value in the range of 2.0-3.8. The second substrate structure also includes a planarized low-K dielectric disposed between the metal interlevel lines and a protective coating separating the metal interlevel lines from the low-K dielectric, the metal interlevel lines having a melting temperature on the order of less than 500.degree. C. and the low-K dielectric having a dielectric K-value in the range of 2.0-3.8. Lastly, the first substrate structure is low temperature bonded to the second substrate structure at respective metal interlevel lines of the first and second substrate structures.

摘要翻译： 高密度集成电路结构及其制造方法包括提供具有根据第一电路实现的半导体器件结构的第一硅衬底结构和设置在其顶表面上的金属层间线以及具有第二电路的第二硅衬底结构 实施和设置在其顶表面上的金属层间线。 第一衬底结构包括设置在金属层间线之间的平面化低K电介质和将金属层间线与低K电介质分开的保护涂层，第一硅衬底结构的金属层间线具有按顺序的熔融温度 小于500℃的低K电介质，介电K值在2.0-3.8范围内。 第二基板结构还包括布置在金属层间线之间的平坦化的低K电介质和将金属层间线与低K电介质隔开的保护涂层，金属层间线具有小于500°的熔融温度 并且介电K值在2.0-3.8范围内的低K电介质。 最后，第一衬底结构在第一和第二衬底结构的相应的金属层间线处被低温地结合到第二衬底结构。

公开(公告)号：US6075268A

公开(公告)日：2000-06-13

申请号：US188972

申请日：1998-11-10

申请人： Mark I. Gardner ,  Daniel Kadosh

发明人： Mark I. Gardner ,  Daniel Kadosh

IPC分类号： H01L21/822 ,  H01L27/06 ,  H01L29/76 ,  H01L23/02 ,  H01L29/94 ,  H01L31/062 ,  H01L31/119

CPC分类号： H01L27/0688 ,  H01L21/8221 ,  H01L2924/0002

摘要： A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds the to the overall circuit density, but does so with emphasis placed on high performance interconnection between devices on separate levels. The interconnect configuration is made as short as possible between features within one transistor level to features within another transistor level. This interconnect scheme lowers resistivity by forming a gate conductor of an upper level transistor upon a gate conductor of lower level transistor. Alternatively, the gate conductors can be a single conductive entity. In order to abut the gate conductors together, or form a single gate conductor, the upper level transistor is inverted relative to the lower level transistor. In addition to the inverted, shared gate conductor, the multi-level transistor fabrication process incorporates formation of openings and filling of those openings to produce interconnect to junctions of the upper/lower transistors. Interconnecting the gate conductors of a pair of stacked transistors and connecting specific junctions of those transistors allows formation of a high density inverter circuit hereof.

摘要翻译： 提供了一种用于在半导体形貌的各种水平上产生有源和无源器件的工艺。 因此，本方法可以实现三维装置的形成，以增强形成集成电路的总体密度。 多级制造工艺不仅增加了整体电路密度，而且重点放在了在不同级别的器件之间的高性能互连。 互连配置在一个晶体管电平内的特征之间尽可能短，在另一个晶体管级内的特征。 该互连方案通过在下级晶体管的栅极导体上形成上层晶体管的栅极导体来降低电阻率。 或者，栅极导体可以是单个导电实体。 为了将栅导体邻接在一起或形成单个栅极导体，上层晶体管相对于下层晶体管反相。 除了反向共享栅极导体之外，多级晶体管制造工艺包括形成开口和填充这些开口以产生与上/下晶体管的结的互连。 将一对堆叠晶体管的栅极导体和这些晶体管的连接特定结之间的互连允许形成其中的高密度反相器电路。

公开(公告)号：US6010957A

公开(公告)日：2000-01-04

申请号：US882423

申请日：1997-06-25

申请人： Mark I. Gardner ,  Daniel Kadosh

发明人： Mark I. Gardner ,  Daniel Kadosh

IPC分类号： H01L21/768 ,  H01L23/528 ,  H01L21/283

CPC分类号： H01L21/76838 ,  H01L23/5283 ,  H01L2924/0002

摘要： A semiconductor device and fabrication process in which tapered conductive lines are formed. Consistent with one embodiment of the invention, a semiconductor device is formed by forming at least one conductive structure over a substrate and forming an insulating layer over the conductive structure. The insulating layer is provided with one or more tapered grooves separated from the conductive structure by a portion of the insulating layer. In each tapered groove a conductive line is formed. The conductive lines may, for example, be metal lines. The conductive structures may, for example, be active regions of a transistor or a previously formed conductive line. A portion of the insulating layer between the conductive layers may be a low dielectric material.

摘要翻译： 形成锥形导电线的半导体器件和制造工艺。 根据本发明的一个实施例，通过在衬底上形成至少一个导电结构并在导电结构上形成绝缘层来形成半导体器件。 绝缘层设置有通过绝缘层的一部分与导电结构分离的一个或多个锥形槽。 在每个锥形槽中形成导线。 导线例如可以是金属线。 导电结构可以例如是晶体管的有源区或者预先形成的导电线。 导电层之间的绝缘层的一部分可以是低电介质材料。

公开(公告)号：US6004849A

公开(公告)日：1999-12-21

申请号：US911745

申请日：1997-08-15

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Michael Duane

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Michael Duane

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/66659 ,  H01L21/28114 ,  H01L29/665 ,  H01L29/7835

摘要： A method of making an asymmetrical IGFET is disclosed. The method includes providing a semiconductor substrate with an active region, wherein the active region includes a source region and a drain region, forming a gate insulator on the active region, forming a gate on the gate insulator and over the active region, implanting arsenic into the active region to provide a greater concentration of arsenic in the source region than in the drain region, growing an oxide layer over the active region, wherein the oxide layer has a greater thickness over the source region than over the drain region due to the greater concentration of arsenic in the source region than in the drain region, forming a source in the source region and a drain in the drain region, depositing a refractory metal over the gate, the source, the drain, and the oxide layer, and reacting the refractory metal with the drain without reacting the refractory metal with the source, thereby forming a silicide contact on the drain without forming a silicide contact on the source. Advantageously, the IGFET has low source-drain resistance, shallow channel junctions, and an LDD that reduces hot carrier effects.

摘要翻译： 公开了制造不对称IGFET的方法。 该方法包括提供具有有源区的半导体衬底，其中有源区包括源极区和漏极区，在有源区上形成栅极绝缘体，在栅极绝缘体上并在有源区上方形成栅极，将砷注入 所述有源区域在所述源极区域中提供比在所述源极区域中更大的砷浓度，在所述有源区域上生长氧化物层，其中所述氧化物层在所述源极区域上比在所述漏极区域上的厚度大于所述漏极区域上的厚度 在源极区域中的砷浓度比漏极区域中的砷浓度高，在源极区域形成源极，在漏极区域形成漏极，在栅极，源极，漏极和氧化物层上沉积难熔金属，并使 具有漏极的难熔金属，而不使难熔金属与源极反应，从而在漏极上形成硅化物接触，而不在源上形成硅化物接触。 有利地，IGFET具有低源极 - 漏极电阻，浅沟道结和降低热载流子效应的LDD。