公开(公告)号：US20130062771A1

公开(公告)日：2013-03-14

申请号：US13405922

申请日：2012-02-27

申请人： Chikaaki KODAMA ,  Koichi Nakayama ,  Toshiya Kotani ,  Shigeki Nojima

发明人： Chikaaki KODAMA ,  Koichi Nakayama ,  Toshiya Kotani ,  Shigeki Nojima

IPC分类号： H01L23/48 ,  H01L21/311 ,  G06F17/50

CPC分类号： H01L21/31144 ,  G06F17/5077 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76816 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a design method of layout formed by a sidewall method is provided. The method includes: preparing a base pattern on which a plurality of first patterns extending in a first direction and arranged at a first space in a second direction intersecting the first direction and a plurality of second patterns extending in the first direction and arranged at a center between the first patterns, respectively, are provided; and drawing a connecting portion which extends in the second direction and connects two neighboring first patterns sandwiching one of the second patterns, and separating the one of the second patterns into two patterns not contacting the connecting portion.

公开(公告)号：US20110201138A1

公开(公告)日：2011-08-18

申请号：US13024604

申请日：2011-02-10

申请人： Shigeki Nojima ,  Tetsuaki Matsunawa ,  Shigeru Hasebe ,  Masahiro Miyairi

发明人： Shigeki Nojima ,  Tetsuaki Matsunawa ,  Shigeru Hasebe ,  Masahiro Miyairi

IPC分类号： H01L21/66 ,  G06F17/50

CPC分类号： G03F1/36 ,  H01L22/12 ,  H01L22/20

摘要： According to a mask verifying method of the embodiment, a difference between an actual dimension of a mask pattern and a simulation dimension is calculated as a computational estimated value. Moreover, a difference between an actual dimension of the mask pattern that is actually measured and a dimension on pattern data is calculated as an actually-measured difference. Then, it is verified whether a mask pattern dimension passes or fails based on the calculated value. When calculating the computational estimated value, a model function, which is set based on each correspondence relationship between an actual dimension and a mask simulation dimension of a test pattern, which includes a plurality of types of pattern ambient environments, to the mask pattern.

摘要翻译： 根据本实施例的掩模验证方法，计算掩模图案的实际尺寸与模拟尺寸之间的差异作为计算估计值。 此外，将实际测量的掩模图案的实际尺寸与图案数据上的尺寸之间的差计算为实际测量的差。 然后，根据计算值验证掩模图案尺寸是否通过或失败。 当计算计算估计值时，将基于包括多种图案环境环境的测试图案的实际尺寸和掩模模拟尺寸之间的每个对应关系设置的模型函数提供给掩模图案。

公开(公告)号：US07934175B2

公开(公告)日：2011-04-26

申请号：US12062859

申请日：2008-04-04

申请人： Toshiya Kotani ,  Yasunobu Kai ,  Soichi Inoue ,  Satoshi Tanaka ,  Shigeki Nojima ,  Kazuyuki Masukawa ,  Koji Hashimoto

发明人： Toshiya Kotani ,  Yasunobu Kai ,  Soichi Inoue ,  Satoshi Tanaka ,  Shigeki Nojima ,  Kazuyuki Masukawa ,  Koji Hashimoto

IPC分类号： G06F17/50

CPC分类号： G03F7/70625 ,  G03F7/70525 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： A parameter adjustment method for a plurality of manufacturing devices to form a pattern of a semiconductor device on a substrate using the manufacturing devices includes: adjusting a parameter adjustable for a manufacturing device serving as a reference manufacturing device; obtaining a first shape of a pattern of a semiconductor device to be formed on a substrate; defining an adjustable parameter of another to-be-adjusted manufacturing; obtaining a second shape of the pattern formed on the substrate; calculating a difference amount between a reference finished shape and a to-be-adjusted finished shape; repeatedly calculating the difference amount by changing the to-be-adjusted parameter until the difference amount becomes equal to or less than a predetermined reference value; and outputting as a parameter of the to-be-adjusted manufacturing device the to-be-adjusted parameter.

摘要翻译： 用于使用该制造装置在基板上形成半导体器件的图案的多个制造装置的参数调整方法包括：调整可用于作为参考制造装置的制造装置的参数; 获得要在基板上形成的半导体器件的图案的第一形状; 定义另一个待调整制造的可调参数; 获得形成在所述基板上的所述图案的第二形状; 计算参考完成形状和待调整完成形状之间的差值; 通过改变待调整参数重复计算差值，直到差值变得等于或小于预定参考值; 并作为待调整制造装置的参数输出待调整参数。

公开(公告)号：US07895541B2

公开(公告)日：2011-02-22

申请号：US11901030

申请日：2007-09-14

申请人： Shigeki Nojima

发明人： Shigeki Nojima

IPC分类号： G06F17/50

CPC分类号： G06T7/001 ,  G03F1/36 ,  G06F17/5081 ,  G06T2207/30148

摘要： A semiconductor integrated circuit pattern verification method includes executing simulation to obtain a simulation pattern to be formed on a substrate on the basis of a semiconductor integrated circuit design pattern, comparing the simulation pattern and the design pattern that is required on the substrate to detect a first difference value, extracting error candidates at which the first difference value is not less than a first predetermined value, comparing pattern shapes at the error candidates to detect a second difference value, combining, into one group, patterns whose second difference values are not more than a second predetermined value, and extracting a predetermined number of patterns from each group and verifying error candidates of the extracted patterns.

摘要翻译： 半导体集成电路图案验证方法包括执行模拟，以基于半导体集成电路设计图案获得要在基板上形成的模拟图案，比较基板上所需的模拟图案和设计图案，以检测第一 差分值，提取第一差值不小于第一预定值的错误候选，比较错误候选的图案形状以检测第二差值，将第二差值不大于 第二预定值，并且从每个组提取预定数量的模式并验证提取的模式的错误候选。

公开(公告)号：US07794897B2

公开(公告)日：2010-09-14

申请号：US11068896

申请日：2005-03-02

申请人： Toshiya Kotani ,  Satoshi Tanaka ,  Shigeki Nojima ,  Koji Hashimoto ,  Soichi Inoue

发明人： Toshiya Kotani ,  Satoshi Tanaka ,  Shigeki Nojima ,  Koji Hashimoto ,  Soichi Inoue

IPC分类号： G03F1/00

CPC分类号： G06F17/5068 ,  G03F1/36

摘要： A pattern correcting method for correcting a design pattern to form a desired pattern on a wafer is disclosed, which comprises defining an allowable dimensional change quantity of each of design patterns, defining a pattern correction condition for the each design pattern based on the allowable dimensional change quantity defined for the each design pattern, and correcting the each design pattern based on the pattern correction condition defined for the each design pattern.

摘要翻译： 公开了一种用于校正在晶片上形成期望图案的设计图案的图案校正方法，其包括限定每个设计图案的允许尺寸变化量，基于允许的尺寸变化来定义每个设计图案的图案校正条件 并且基于为每个设计图案定义的图案校正条件来校正每个设计图案。

公开(公告)号：US20090265680A1

公开(公告)日：2009-10-22

申请号：US12457751

申请日：2009-06-19

申请人： Kyoko Izuha ,  Shigeki Nojima ,  Toshiya Kotani ,  Satoshi Tanaka

发明人： Kyoko Izuha ,  Shigeki Nojima ,  Toshiya Kotani ,  Satoshi Tanaka

IPC分类号： G06F17/50

CPC分类号： G03F7/70441 ,  G03F1/36

摘要： A pattern verification method comprising preparing a desired pattern and a mask pattern forming the desired pattern on a substrate, defining at least one evaluation point on an edge of the desired pattern, defining at least one process parameter to compute the transferred/formed pattern, defining a reference value and a variable range for each of the process parameters, computing a positional displacement for each first points corresponding to the evaluation point, first points computed using correction mask pattern and a plurality of combinations of parameter values obtained by varying the process parameters within the variable range or within the respective variable ranges, the positional displacement being displacement between first point and the evaluation point, computing a statistics of the positional displacements for each of the evaluation points, and outputting information modifying the mask pattern according to the statistics.

摘要翻译： 一种图案验证方法，包括在衬底上制备期望图案和形成期望图案的掩模图案，在期望图案的边缘上限定至少一个评估点，限定至少一个工艺参数以计算所转印/形成的图案，定义 对于每个过程参数的参考值和可变范围，计算与评估点相对应的每个第一点的位置位移，使用校正掩模图案计算的第一点和通过改变其中的处理参数而获得的参数值的多个组合 可变范围或在各个可变范围内，位置偏移是第一点和评估点之间的位移，计算每个评估点的位置偏移的统计，以及根据统计信息输出修改掩模图案的信息。

公开(公告)号：US07526748B2

公开(公告)日：2009-04-28

申请号：US11200176

申请日：2005-08-10

申请人： Toshiya Kotani ,  Satoshi Tanaka ,  Shigeki Nojima ,  Soichi Inoue

发明人： Toshiya Kotani ,  Satoshi Tanaka ,  Shigeki Nojima ,  Soichi Inoue

IPC分类号： G06F17/50

CPC分类号： H01J37/3026 ,  G03F1/36 ,  G03F1/68

摘要： A design pattern data preparing method including preparing first mask pattern data based on first design pattern data, predicting a wafer pattern to be formed on a wafer corresponding to the first mask pattern based on the first mask pattern data, judging whether or not a finite difference between the predicted wafer pattern and the pattern to be formed on the wafer is within a predetermined allowable variation amount, correcting a portion of the first design pattern data selectively, the portion including a part corresponding to the finite difference when the finite difference is not within the allowable variation amount, and preparing second design pattern data by synthesizing the first mask pattern data corresponding to the portion including the part selectively corrected and data obtained by eliminating the first mask pattern data corresponding to the portion including the part selectively corrected from the first mask pattern data.

摘要翻译： 一种设计图案数据准备方法，包括基于第一设计图案数据准备第一掩模图案数据，基于第一掩模图案数据预测在与第一掩模图案相对应的晶片上形成的晶片图案，判断是否存在有限差 在预定的晶片图案和要在晶片上形成的图案之间的预定容许变化量在预定的允许变化量中，选择性地校正第一设计图案数据的一部分，当有限差不在内部时，包括对应于有限差的部分 通过合成对应于包括选择性校正的部分的部分的第一掩模图案数据和通过消除与包括从第一掩模选择性校正的部分相对应的部分的第一掩模图案数据而获得的数据来准备第二设计图案数据 模式数据。

公开(公告)号：US20080250381A1

公开(公告)日：2008-10-09

申请号：US12062859

申请日：2008-04-04

申请人： Toshiya KOTANI ,  Yasunobu Kai ,  Soichi Inoue ,  Satoshi Tanaka ,  Shigeki Nojima ,  Kazuyuki Masukawa ,  Koji Hashimoto

发明人： Toshiya KOTANI ,  Yasunobu Kai ,  Soichi Inoue ,  Satoshi Tanaka ,  Shigeki Nojima ,  Kazuyuki Masukawa ,  Koji Hashimoto

IPC分类号： G06F17/50

CPC分类号： G03F7/70625 ,  G03F7/70525 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： A parameter adjustment method for a plurality of manufacturing devices to form a pattern of a semiconductor device on a substrate using the manufacturing devices includes: adjusting a parameter adjustable for a manufacturing device serving as a reference manufacturing device so as to fall within a range of a predetermined permissible variation and defining the adjusted parameter as a reference parameter of the reference manufacturing device; obtaining a first shape of a pattern of a semiconductor device to be formed on a substrate using the reference manufacturing device from a mask to form the pattern on the substrate when the reference parameter is set to the reference manufacturing device and defining the obtained first shape as a reference finished shape; defining an adjustable parameter of another to-be-adjusted manufacturing device as a to-be-adjusted parameter of the to-be-adjusted manufacturing device; obtaining a second shape of the pattern formed on the substrate using the to-be-adjusted manufacturing device from the mask when the defined to-be-adjusted parameter is set to the to-be-adjusted manufacturing device and defining the obtained second shape as a to-be-adjusted finished shape; calculating a difference amount between the reference finished shape and the to-be-adjusted finished shape; repeatedly calculating the difference amount by changing the to-be-adjusted parameter until the difference amount becomes equal to or less than a predetermined reference value; outputting as a parameter of the to-be-adjusted manufacturing device the to-be-adjusted parameter having the difference amount equal to or less than the predetermined reference value or the to-be-adjusted parameter having the difference amount which becomes equal to or less than the predetermined reference value through the repeated calculation.

摘要翻译： 用于使用该制造装置在基板上形成半导体器件的图案的多个制造装置的参数调整方法包括：调整作为参考制造装置的制造装置可调节的参数，使其落在 预定的允许变化并将调整参数定义为参考制造装置的参考参数; 使用参考制造装置从掩模获得要在基板上形成的半导体器件的图案的第一形状，以在将参考参数设置为参考制造装置并将所获得的第一形状定义为 参考完成形状; 将另一个待调节制造装置的可调参数定义为待调整制造装置的待调整参数; 当将所述规定的待调整参数设定为所述待调节制造装置并且将所获得的第二形状定义为所述第二形状时，从所述掩模获得使用所述待调节制造装置在所述基板上形成的所述图案的第二形状 一个待调整的成品形状; 计算参考完成形状和待调整完成形状之间的差值; 通过改变待调整参数重复计算差值，直到差值变得等于或小于预定参考值; 作为待调整制造装置的参数输出具有等于或小于预定参考值的差值的待调整参数或具有等于或等于或等于或等于 通过重复计算小于预定的参考值。

公开(公告)号：US20050273754A1

公开(公告)日：2005-12-08

申请号：US11138407

申请日：2005-05-27

申请人： Shigeki Nojima ,  Satoshi Tanaka ,  Toshiya Kotani ,  Kyoko Izuha ,  Soichi Inoue

发明人： Shigeki Nojima ,  Satoshi Tanaka ,  Toshiya Kotani ,  Kyoko Izuha ,  Soichi Inoue

IPC分类号： G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  G03F7/20 ,  G06F17/50 ,  G21K5/10 ,  H01L21/027

CPC分类号： G03F1/36

摘要： A pattern data correction method is disclosed, which comprises preparing an integrated circuit pattern, setting a tolerance to the pattern that is allowable error range when the pattern is transferred on a substrate, creating a target pattern within the tolerance, and making correction for the target pattern to make a first correction pattern under a predetermined condition.

摘要翻译： 公开了一种图案数据校正方法，其包括：准备集成电路图案，在图案在衬底上传送时设定容许误差范围的容许度，在公差内产生目标图案，并对目标进行校正 模式以在预定条件下进行第一校正模式。

公开(公告)号：US06334209B1

公开(公告)日：2001-12-25

申请号：US09389090

申请日：1999-09-02

申请人： Koji Hashimoto ,  Shigeki Nojima

发明人： Koji Hashimoto ,  Shigeki Nojima

IPC分类号： G06F1750

CPC分类号： G03F1/84

摘要： Disclosed is an exposure mask inspecting method for use in manufacturing semiconductor devices. This inspecting method calculate gradients of a correlation curve of a variation in critical dimension of an exposure mask and a variation in critical dimension of a resist, extracts portions having large slopes of the correlation curve, and slopes the portions having large slopes of the correlation curve as to-be-measured portions at the time of verifying the specifications of the surface critical dimension of the exposure mask.

摘要翻译： 公开了一种用于制造半导体器件的曝光掩模检查方法。 该检查方法计算曝光掩模的临界尺寸的变化与抗蚀剂的临界尺寸的变化的相关曲线的梯度，提取具有相关曲线的大斜率的部分，并且使具有相关曲线的大斜率的部分倾斜 作为在验证曝光掩模的表面临界尺寸的规格时的待测量部分。