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    MUSHROOM TYPE MEMORY CELL HAVING SELF-ALIGNED BOTTOM ELECTRODE AND DIODE ACCESS DEVICE
    42.
    发明申请
    MUSHROOM TYPE MEMORY CELL HAVING SELF-ALIGNED BOTTOM ELECTRODE AND DIODE ACCESS DEVICE 审中-公开
    具有自对准底部电极和二极管访问装置的MUSHROOM型存储单元

    公开(公告)号：US20100019215A1

    公开(公告)日：2010-01-28

    申请号：US12177435

    申请日：2008-07-22

    申请人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Thomas D. Happ ,  Matthew J. Breitwisch ,  Alejandro Gabriel Schrott ,  Min Yang

    发明人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Thomas D. Happ ,  Matthew J. Breitwisch ,  Alejandro Gabriel Schrott ,  Min Yang

    IPC分类号： H01L47/00 ,  H01L21/00

    CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

    摘要： Memory devices are described along with methods for manufacturing. A memory device as described herein includes a plurality of word lines extending in a first direction, and a plurality of bit lines overlying the plurality of word lines and extending in a second direction. A plurality of memory cells are at cross-point locations. Each memory cell comprises a diode having first and second sides aligned with sides of a corresponding word line. Each memory cell also includes a bottom electrode self-centered on the diode, the bottom electrode having a top surface with a surface area less than that of the top surface of the diode. Each of the memory cells includes a strip of memory material on the top surface of the bottom electrode, the strip of memory material underlying and in electrical communication with a corresponding bit line.

    摘要翻译： 描述存储器件以及制造方法。 如本文所述的存储器件包括沿第一方向延伸的多个字线和覆盖多个字线并沿第二方向延伸的多个位线。 多个存储单元处于交叉点位置。 每个存储单元包括具有与相应字线的侧面对准的第一和第二侧的二极管。 每个存储单元还包括以二极管为中心的底部电极，底部电极具有表面积小于二极管顶表面的顶表面。 每个存储器单元包括在底部电极的顶表面上的存储器材料条，存储器材料条下面并与相应位线电连通。

    Phase Change Memory Cell Having Vertical Channel Access Transistor
    43.
    发明申请
    Phase Change Memory Cell Having Vertical Channel Access Transistor 有权
    具有垂直通道访问晶体管的相变存储单元

    公开(公告)号：US20100295123A1

    公开(公告)日：2010-11-25

    申请号：US12471301

    申请日：2009-05-22

    申请人： Hsiang-Lan Lung ,  Chung H. Lam

    发明人： Hsiang-Lan Lung ,  Chung H. Lam

    IPC分类号： H01L27/082 ,  H01L21/336

    CPC分类号： H01L27/101 ,  G11C13/0004 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

    摘要： Memory devices are described along with methods for manufacturing. A device as described herein includes a substrate having a first region and a second region. The first region comprises a first field effect transistor comprising first and second doped regions separated by a horizontal channel region within the substrate, a gate overlying the horizontal channel region, and a first dielectric covering the gate of the first field effect transistor. The second region of the substrate includes a second field effect transistor comprising a first terminal extending through the first dielectric to contact the substrate, a second terminal overlying the first terminal and having a top surface, and a vertical channel region separating the first and second terminals. The second field effect transistor also includes a gate on the first dielectric and adjacent the vertical channel region, the gate having a top surface that is co-planar with the top surface of the second terminal. A second dielectric separates the gate of the second field effect transistor from the vertical channel region.

    摘要翻译： 描述存储器件以及制造方法。 如本文所述的器件包括具有第一区域和第二区域的衬底。 第一区域包括第一场效应晶体管，其包括由衬底内的水平沟道区域分隔的第一和第二掺杂区域，覆盖在水平沟道区域上的栅极和覆盖第一场效应晶体管的栅极的第一电介质。 衬底的第二区域包括第二场效应晶体管，其包括延伸穿过第一电介质以接触衬底的第一端子，覆盖第一端子并具有顶表面的第二端子和分离第一和第二端子的垂直沟道区域 。 第二场效应晶体管还包括在第一电介质上并且与垂直沟道区相邻的栅极，栅极具有与第二端子的顶表面共面的顶表面。 第二电介质将第二场效应晶体管的栅极与垂直沟道区分开。

    PHASE CHANGE MEMORY CELL HAVING VERTICAL CHANNEL ACCESS TRANSISTOR
    45.
    发明申请
    PHASE CHANGE MEMORY CELL HAVING VERTICAL CHANNEL ACCESS TRANSISTOR 有权
    具有垂直通道访问晶体管的相变存储器单元

    公开(公告)号：US20110217818A1

    公开(公告)日：2011-09-08

    申请号：US13110197

    申请日：2011-05-18

    申请人： Hsiang-Lan Lung ,  Chung H. Lam

    发明人： Hsiang-Lan Lung ,  Chung H. Lam

    IPC分类号： H01L21/336

    CPC分类号： H01L27/101 ,  G11C13/0004 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

    摘要： A device includes a substrate having a first region and a second region. The first region comprises a first field effect transistor having a horizontal channel region within the substrate, a gate overlying the horizontal channel region, and a first dielectric covering the gate of the first field effect transistor. The second region of the substrate includes a second field effect transistor comprising a first terminal extending through the first dielectric to contact the substrate, a second terminal overlying the first terminal and having a top surface, and a vertical channel region separating the first and second terminals. The second field effect transistor also includes a gate on the first dielectric and adjacent the vertical channel region, the gate having a top surface that is co-planar with the top surface of the second terminal.

    摘要翻译： 一种器件包括具有第一区域和第二区域的衬底。 第一区域包括在衬底内具有水平沟道区的第一场效应晶体管，覆盖在水平沟道区上的栅极和覆盖第一场效应晶体管的栅极的第一电介质。 衬底的第二区域包括第二场效应晶体管，其包括延伸穿过第一电介质以接触衬底的第一端子，覆盖第一端子并具有顶表面的第二端子和分离第一和第二端子的垂直沟道区域 。 第二场效应晶体管还包括在第一电介质上并且与垂直沟道区相邻的栅极，栅极具有与第二端子的顶表面共面的顶表面。

    Phase Change Memory Cells Having Vertical Channel Access Transistor and Memory Plane
    46.
    发明申请
    Phase Change Memory Cells Having Vertical Channel Access Transistor and Memory Plane 有权
    具有垂直通道访问晶体管和存储器平面的相变存储单元

    公开(公告)号：US20100295009A1

    公开(公告)日：2010-11-25

    申请号：US12471287

    申请日：2009-05-22

    申请人： Hsiang-Lan Lung ,  Chung H. Lam ,  Ming-Hsiu Lee ,  Bipin Rajendran

    发明人： Hsiang-Lan Lung ,  Chung H. Lam ,  Ming-Hsiu Lee ,  Bipin Rajendran

    IPC分类号： H01L47/00 ,  H01L21/00

    CPC分类号： H01L27/101 ,  G11C13/0004 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

    摘要： Memory devices are described along with methods for manufacturing. A memory device as described herein comprises a plurality of word lines overlying a plurality of bit lines, and a plurality of field effect transistors. Field effect transistors in the plurality of field effect transistors comprises a first terminal electrically coupled to a corresponding bit line in the plurality of bit lines, a second terminal overlying the first terminal, and a channel region separating the first and second terminals and adjacent a corresponding word line in the plurality of word lines. The corresponding word line acts as the gate of the field effect transistor. A dielectric separates the corresponding word line from the channel region. A memory plane comprises programmable resistance memory material electrically coupled to respective second terminals of the field effect transistors, and conductive material on the programmable resistance memory material and coupled to a common voltage.

    摘要翻译： 描述存储器件以及制造方法。 如本文所述的存储器件包括覆盖多个位线的多个字线和多个场效应晶体管。 多个场效应晶体管中的场效应晶体管包括电耦合到多个位线中的对应位线的第一端子，覆盖第一端子的第二端子和分离第一和第二端子并且相邻 多行字线中的字线。 相应的字线用作场效应晶体管的栅极。 电介质将对应的字线与沟道区分开。 存储器平面包括电耦合到场效应晶体管的相应第二端子的可编程电阻存储器材料，以及可编程电阻存储器材料上的导体材料并耦合到公共电压。

    Polysilicon plug bipolar transistor for phase change memory
    47.
    发明授权
    Polysilicon plug bipolar transistor for phase change memory 有权
    用于相变存储器的多晶硅插头双极晶体管

    公开(公告)号：US08237144B2

    公开(公告)日：2012-08-07

    申请号：US13252152

    申请日：2011-10-03

    申请人： Hsiang-Lan Lung ,  Erh-Kun Lai ,  Bipin Rajendran ,  Chung H. Lam

    发明人： Hsiang-Lan Lung ,  Erh-Kun Lai ,  Bipin Rajendran ,  Chung H. Lam

    IPC分类号： H01L29/02

    CPC分类号： H01L45/04 ,  G11C13/0004 ,  H01L27/1026 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

    摘要： Memory devices and methods for manufacturing are described herein. A memory device described herein includes a plurality of memory cells. Memory cells in the plurality of memory cells comprise respective bipolar junction transistors and memory elements. The bipolar junction transistors are arranged in a common collector configuration and include an emitter comprising doped polysilicon having a first conductivity type, the emitter contacting a corresponding word line in a plurality of word lines to define a pn junction. The bipolar junction transistors include a portion of the corresponding word line underlying the emitter acting as a base, and a collector comprising a portion of the single-crystalline substrate underlying the base.

    摘要翻译： 本文描述了存储器件和制造方法。 本文描述的存储器件包括多个存储器单元。 多个存储单元中的存储单元包括相应的双极结型晶体管和存储元件。 双极结晶体管被布置成共同的集电极配置，并且包括发射器，其包括具有第一导电类型的掺杂多晶硅，发射极接触多个字线中的对应字线以限定pn结。 双极结晶体管包括作为基极的发射极下面的相应字线的一部分，以及包含基底下方的单晶衬底的一部分的集电极。

    Polysilicon Plug Bipolar Transistor For Phase Change Memory
    48.
    发明申请
    Polysilicon Plug Bipolar Transistor For Phase Change Memory 有权
    用于相变存储器的多晶硅插头双极晶体管

    公开(公告)号：US20120018845A1

    公开(公告)日：2012-01-26

    申请号：US13252152

    申请日：2011-10-03

    申请人： Hsiang-Lan Lung ,  Erh-Kun Lai ,  Bipin Rajendran ,  Chung H. Lam

    发明人： Hsiang-Lan Lung ,  Erh-Kun Lai ,  Bipin Rajendran ,  Chung H. Lam

    IPC分类号： H01L29/73

    CPC分类号： H01L45/04 ,  G11C13/0004 ,  H01L27/1026 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

    摘要： Memory devices and methods for manufacturing are described herein. A memory device described herein includes a plurality of memory cells. Memory cells in the plurality of memory cells comprise respective bipolar junction transistors and memory elements. The bipolar junction transistors are arranged in a common collector configuration and include an emitter comprising doped polysilicon having a first conductivity type, the emitter contacting a corresponding word line in a plurality of word lines to define a pn junction. The bipolar junction transistors include a portion of the corresponding word line underlying the emitter acting as a base, and a collector comprising a portion of the single-crystalline substrate underlying the base.

    摘要翻译： 本文描述了存储器件和制造方法。 本文描述的存储器件包括多个存储器单元。 多个存储单元中的存储单元包括相应的双极结型晶体管和存储元件。 双极结晶体管被布置成共同的集电极配置，并且包括发射器，其包括具有第一导电类型的掺杂多晶硅，发射极接触多个字线中的对应字线以限定pn结。 双极结晶体管包括作为基极的发射极下面的相应字线的一部分，以及包含基底下方的单晶衬底的一部分的集电极。