公开(公告)号：US11917045B2

公开(公告)日：2024-02-27

申请号：US17871937

申请日：2022-07-24

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Arnon Sattinger ,  Natan Manevich ,  Wojciech Wasko ,  Ariel Almog ,  Bar Or Shapira

IPC: H03L7/08 ,  G06F1/12 ,  H04L7/00

CPC classification number: H04L7/0012

Abstract: In one embodiment, a communication system includes network devices, each comprising a network interface to receive at least one data stream, a given network device being configured to recover a remote clock from the at least one data stream received by the given network device, a frequency synthesizer to generate a clock signal and output the clock signal to each of the network devices, wherein the given network device is configured to find a clock frequency differential between the clock signal and the recovered remote clock, and provide a control signal to the frequency synthesizer responsively to the clock frequency differential, the control signal causes the frequency synthesizer to adjust the clock signal so as to iteratively reduce an absolute value of the clock frequency differential between the clock signal and the recovered remote clock.

公开(公告)号：US20240015419A1

公开(公告)日：2024-01-11

申请号：US17869932

申请日：2022-07-21

Applicant: Mellanox Technologies, Ltd.

Inventor： Ioannis (Giannis) Patronas ,  Dotan David Levi ,  Wojciech Wasko ,  Paraskevas Bakopoulos ,  Dimitrios Syrivelis ,  Elad Mentovich

IPC: H04Q11/00 ,  H04B10/2575

CPC classification number: H04Q11/0005 ,  H04B10/25753 ,  H04Q2011/0045 ,  H04Q2011/005

Abstract: Network devices and associated methods are provided for synchronization in an optically switched network. The network device includes one or more ports in communication with a plurality of devices via an optical switch. The one or more ports receive a master clock signal having a first frequency from a first device of the plurality of devices. The network device includes a local clock in communication with the one or more ports and operating at a second frequency. The network device includes a synchronization manager in communication with the one or more ports and the local clock and configured to be enabled and disabled. When the synchronization manager is enabled, it receives the master clock signal via the one or more ports and transmits an instruction to the local clock to operate at the first frequency.

公开(公告)号：US20230370305A1

公开(公告)日：2023-11-16

申请号：US17885604

申请日：2022-08-11

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Ariel Almog ,  Bar Shapira

IPC: H04L12/42 ,  G06F1/10 ,  H04L12/43 ,  H04J3/06

CPC classification number: H04L12/422 ,  G06F1/10 ,  H04J3/0667 ,  H04L12/43

Abstract: In one embodiment, a synchronized communication system includes a plurality of network devices, and clock connections to connect the network devices in a closed loop configuration, wherein the network devices are configured to distribute among the network devices a reference clock time from any selected one of the network devices.

公开(公告)号：US11711158B2

公开(公告)日：2023-07-25

申请号：US17359667

申请日：2021-06-28

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Wojciech Wasko ,  Natan Manevich ,  Hillel Chapman ,  Roi Geuli ,  Eyal Serbro

IPC: H04J3/06

CPC classification number: H04J3/0661 ,  H04J3/062

Abstract: A network device includes a port, a transmission pipeline and a time-stamping circuit. The port is configured for connecting to a network. The transmission pipeline includes multiple pipeline stages and is configured to process packets and to send the packets to the network via the port. The time-stamping circuit is configured to temporarily suspend at least some processing of at least a given packet in the transmission pipeline, to verify whether a pipeline stage having a variable processing delay, located downstream from the time-stamping circuit, meets an emptiness condition, and, only when the pipeline stage meets the emptiness condition, to time-stamp the given packet and resume the processing of the given packet.

公开(公告)号：US11706014B1

公开(公告)日：2023-07-18

申请号：US17579630

申请日：2022-01-20

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Ariel Almog ,  Bar Shapira

IPC: H04L7/00

CPC classification number: H04L7/0012

Abstract: In one embodiment, a synchronized communication system includes a plurality of compute nodes, and clock connections to connect the compute nodes in a closed loop configuration, wherein the compute nodes are configured to distribute among the compute nodes a master clock frequency from any selected one of the compute nodes.

公开(公告)号：US20230185600A1

公开(公告)日：2023-06-15

申请号：US17549949

申请日：2021-12-14

Applicant: Mellanox Technologies, Ltd.

Inventor： Wojciech Wasko ,  Dotan David Levi ,  Liron Mula ,  Natan Manevich

IPC: G06F9/48 ,  G06F13/16 ,  G06F1/08

CPC classification number: G06F9/4825 ,  G06F9/485 ,  G06F13/1689 ,  G06F1/08

Abstract: In one embodiment, a system includes a memory, a processing device including a device processor; and a device clock, and a peripheral device including an interface to share data with the processing device, a hardware clock, and processing circuitry to write respective interrupt signaling messages to the memory responsively to respective hardware clock values of the hardware clock, and wherein the device processor is configured, responsively to the respective interrupt signaling messages being written to the memory, to perform a time-dependent action.

公开(公告)号：US11606157B1

公开(公告)日：2023-03-14

申请号：US17520674

申请日：2021-11-07

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Wojciech Wasko ,  Dotan David Levi ,  Guy Lederman

IPC: H04J3/06 ,  H04L43/06 ,  H04L43/065 ,  H04L43/067

Abstract: A network node includes a port and circuitry. The port is configured for communicating over a packet network. The circuitry is configured to receive, via the port, a sequence of packets from a peer network node, the sequence of packets including (i) a time-protocol packet and (ii) a transmit-side (TX) time-stamp indicative of a time at which the time-protocol packet was transmitted from the peer network node, to assess a receive-side (RX) traffic pattern over one or more of the received packets in the sequence that precede reception of the time-protocol packet, and to calculate an accuracy measure for the TX time-stamp, based on the assessed RX traffic pattern.

公开(公告)号：US20220360423A1

公开(公告)日：2022-11-10

申请号：US17315396

申请日：2021-05-10

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Wojciech Wasko ,  Natan Manevich ,  Teferet Geula ,  Amit Mandelbaum ,  Ariel Almog

IPC: H04L7/00 ,  H04L12/26 ,  G06N20/00

Abstract: In one embodiment, a processing apparatus includes processing circuitry to process an event, a timestamping unit to generate a timestamp for the event, at least one register to store at least one parameter describing a hardware state of the processing circuitry, and timestamp correction processing circuitry to compute a time value as a correction to the generated timestamp responsively to the at least one parameter.

公开(公告)号：US20220352998A1

公开(公告)日：2022-11-03

申请号：US17246730

申请日：2021-05-03

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Wojciech Wasko ,  Natan Manevich ,  Roee Moyal ,  Eliel Peretz ,  Eran Ben Elisha ,  Ariel Almog ,  Teferet Geula ,  Amit Mandelbaum

IPC: H04J3/06 ,  H04L12/26 ,  H04L29/08

Abstract: In one embodiment, an event processing system includes a clock configured to provide time values, and event processing circuitry, which is configured to generate a confidence level indicative of a degree of confidence of an accuracy of a timestamp, the timestamp being generated for an event responsively to a time value indicative of when an operation associated with the event occurred.