公开(公告)号：US06226223B1

公开(公告)日：2001-05-01

申请号：US09511901

申请日：2000-02-23

申请人： Masanori Shirahama ,  Tsutomu Fujita ,  Masashi Agata ,  Kazunari Takahashi ,  Naoki Kuroda

发明人： Masanori Shirahama ,  Tsutomu Fujita ,  Masashi Agata ,  Kazunari Takahashi ,  Naoki Kuroda

IPC分类号： G11C800

CPC分类号： G11C7/222 ,  G11C7/22 ,  G11C11/24 ,  G11C11/4076

摘要： In a semiconductor memory device with multiple memory cells, each including a charge storage device and two transfer devices for transferring its charge, these memory cells are accessible with no select signal provided externally. The memory device includes a clock generator for generating first and second mutually complementary clock signals. In response to the first and second clock signals, one of first word lines and one of second word lines are activated alternately. Specifically, the first clock signal makes a memory cell accessible through a first bit line by activating the first word line and first transistor, while the second clock signal makes the memory cell accessible through a second bit line by activating the second word line and second transistor.

摘要翻译： 在具有多个存储器单元的半导体存储器件中，每个存储单元包括一个电荷存储器件和两个用于传送其电荷的转移器件，这些存储器单元是可以被访问的，没有从外部提供的选择信号。 存储器件包括用于产生第一和第二互补时钟信号的时钟发生器。 响应于第一和第二时钟信号，交替地激活第一字线和第二字线之一中的一个。 具体地，第一时钟信号通过激活第一字线和第一晶体管使得可通过第一位线访问存储单元，而第二时钟信号通过激活第二字线和第二晶体管使存储单元通过第二位线访问 。

公开(公告)号：US06181620B2

公开(公告)日：2001-01-30

申请号：US09484023

申请日：2000-01-18

申请人： Masashi Agata ,  Kazunari Takahashi ,  Tsutomu Fujita ,  Naoki Kuroda ,  Toshio Yamada

发明人： Masashi Agata ,  Kazunari Takahashi ,  Tsutomu Fujita ,  Naoki Kuroda ,  Toshio Yamada

IPC分类号： G11C1124

CPC分类号： G11C11/405 ,  G11C7/1042 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4091 ,  G11C11/4094

摘要： The semiconductor storage device of this invention includes memory cells each having two transistors and one storage capacitor. Each memory cell is connected with a first word line and a first bit line for a first port and a second word line and a second bit line for a second port. The first and second bit lines are alternately disposed in an open bit line configuration. In the operation of the semiconductor storage device, in a period when a first precharge signal for precharging each first bit line or a first sense amplifier activating signal for activating a first sense amplifier is kept in an active state, a second precharge signal for precharging each second bit line and a second sense amplifier activating signal for activating a second sense amplifier are both placed in an inactive state.

摘要翻译： 本发明的半导体存储装置包括具有两个晶体管和一个存储电容器的存储单元。 每个存储单元与第一字线和用于第一端口的第一位线和用于第二端口的第二字线和第二位线连接。 第一位线和第二位线以开放位线配置交替布置。 在半导体存储装置的动作中，在对第一读出放大器的第一预定电荷进行预充电的第一预充电信号或激活第一读出放大器的第一读出放大器的激活信号保持为有效状态的期间内， 第二位线和用于激活第二读出放大器的第二读出放大器激活信号都处于非活动状态。

公开(公告)号：US06169684A

公开(公告)日：2001-01-02

申请号：US09495473

申请日：2000-02-01

申请人： Kazunari Takahashi ,  Masashi Agata ,  Naoki Kuroda ,  Tsutomu Fujita

发明人： Kazunari Takahashi ,  Masashi Agata ,  Naoki Kuroda ,  Tsutomu Fujita

IPC分类号： G11C1500

CPC分类号： G11C11/4097 ,  G06F12/0893 ,  G06F2212/3042 ,  G11C11/005

摘要： A cache memory including a first memory array and a main memory including a second memory array are integrated together on the same semiconductor substrate. Each memory cell in the first memory array is of a 2Tr1C type including: first and second transistors, the sources of which are connected together; and a data storage capacitor, one of the two electrodes of which is connected to the common source of the first and second transistors. Each memory cell in the second memory array is of a 1Tr1C type including: a third transistor; and a data storage capacitor, one of the two electrodes of which is connected to the source of the third transistor.

摘要翻译： 包括第一存储器阵列和包括第二存储器阵列的主存储器的高速缓存存储器集成在同一半导体衬底上。 第一存储器阵列中的每个存储单元是2Tr1C类型，包括：第一和第二晶体管，其源极连接在一起; 以及数据存储电容器，其两个电极中的一个连接到第一和第二晶体管的公共源。 第二存储器阵列中的每个存储单元是1Tr1C类型，包括：第三晶体管; 以及数据存储电容器，其两个电极中的一个连接到第三晶体管的源极。

公开(公告)号：US5204653A

公开(公告)日：1993-04-20

申请号：US643949

申请日：1991-01-22

申请人： Susumu Saitoh ,  Tetsurou Itoh ,  Naoki Kuroda

发明人： Susumu Saitoh ,  Tetsurou Itoh ,  Naoki Kuroda

IPC分类号： H01F27/26

CPC分类号： H01F27/263

摘要： An electromagnetic induction device which comprises a split-type core assembly comprising at least one winding formed thereon and first and second core segments each having at least two joint faces spaced apart from each other, the first and second core segments are connected together with the joint faces of one of the first and second core segments held in contact with the joint faces of the other of the first and second core segments, and a finely divided ferromagnetic material is interposed between the joint faces of the respective first and second core segments. The ferromagnetic material used has an average particle size sufficient to form a magnetic fluid medium.

摘要翻译： 一种电磁感应装置，包括分开型芯组件，其包括形成在其上的至少一个绕组，以及第一和第二芯段，每个芯段具有彼此间隔开的至少两个接合面，第一和第二芯段与接头连接在一起 第一和第二芯部段之一的表面与第一和第二芯段中另一个的接合面保持接触，并且在相应的第一和第二芯部段的接合面之间插入细分的铁磁材料。 使用的铁磁材料具有足以形成磁性流体介质的平均粒径。