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公开(公告)号：US06226223B1
公开(公告)日：2001-05-01
申请号：US09511901
申请日：2000-02-23
IPC分类号： G11C800
CPC分类号： G11C7/222 , G11C7/22 , G11C11/24 , G11C11/4076
摘要： In a semiconductor memory device with multiple memory cells, each including a charge storage device and two transfer devices for transferring its charge, these memory cells are accessible with no select signal provided externally. The memory device includes a clock generator for generating first and second mutually complementary clock signals. In response to the first and second clock signals, one of first word lines and one of second word lines are activated alternately. Specifically, the first clock signal makes a memory cell accessible through a first bit line by activating the first word line and first transistor, while the second clock signal makes the memory cell accessible through a second bit line by activating the second word line and second transistor.
摘要翻译： 在具有多个存储器单元的半导体存储器件中，每个存储单元包括一个电荷存储器件和两个用于传送其电荷的转移器件，这些存储器单元是可以被访问的，没有从外部提供的选择信号。 存储器件包括用于产生第一和第二互补时钟信号的时钟发生器。 响应于第一和第二时钟信号，交替地激活第一字线和第二字线之一中的一个。 具体地，第一时钟信号通过激活第一字线和第一晶体管使得可通过第一位线访问存储单元，而第二时钟信号通过激活第二字线和第二晶体管使存储单元通过第二位线访问 。
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公开(公告)号：US06788565B2
公开(公告)日：2004-09-07
申请号：US10394262
申请日：2003-03-24
申请人： Masashi Agata , Kazunari Takahashi , Masanori Shirahama , Naoki Kuroda , Hiroyuki Sadakata , Ryuji Nishihara
发明人： Masashi Agata , Kazunari Takahashi , Masanori Shirahama , Naoki Kuroda , Hiroyuki Sadakata , Ryuji Nishihara
IPC分类号： G11C1140
CPC分类号： G11C11/405 , H01L27/108
摘要： A semiconductor memory device has a plurality of memory cells each having a first transistor, a second transistor having a source or drain connected to one portion of the source or drain of the first transistor, and a third transistor having a source or drain connected to the other portion of the source or drain of the first transistor. The first transistor accumulates, in the channel thereof, charges transferred from the second and third transistors.
摘要翻译： 半导体存储器件具有多个存储单元，每个存储单元具有第一晶体管，第二晶体管具有连接到第一晶体管的源极或漏极的一部分的源极或漏极;以及第三晶体管，源极或漏极连接到第一晶体管， 第一晶体管的源极或漏极的另一部分。 第一晶体管在其通道中累积从第二和第三晶体管传送的电荷。
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公开(公告)号：US07203117B2
公开(公告)日：2007-04-10
申请号：US11245075
申请日：2005-10-07
IPC分类号： G11C17/18
CPC分类号： G11C17/18
摘要： A fuse device and a program transistor are connected in series with each other. A flip-flop turns ON, in response to a start signal, the program transistor to start program of the fuse device. A 2-input NAND circuit outputs an end signal at a time point where change in a resistance value of the fuse device is increased to reach a predetermined level while monitoring change in the resistance value of the fuse device through change in a voltage at a junction point of the fuse device and the program transistor. The flip-flop turns OFF, in response to the end signal, the program transistor to automatically terminate the program of the fuse device. Thus, the resistance value of the fuse device is increased to the predetermined level in a minimum program time.
摘要翻译： 熔丝器件和程序晶体管彼此串联连接。 触发器响应于启动信号而导通，程序晶体管开始保险丝装置的编程。 2输入NAND电路在熔断器件的电阻值的变化增加以达到预定值的时间点输出结束信号，同时通过接点处的电压变化来监测熔丝器件的电阻值的变化 保险丝装置和程序晶体管的点。 触发器关闭，响应于结束信号，程序晶体管自动终止保险丝装置的程序。 因此，保险丝装置的电阻值在最小程序时间内增加到预定电平。
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公开(公告)号：US07200025B2
公开(公告)日：2007-04-03
申请号：US11272818
申请日：2005-11-15
IPC分类号： G11C17/00
摘要： Selection signals output from a decoder are selectively set at High according to the states (blown or not blown) or fuses in bit cells in a cell group specifying circuit. Then, one of transistor gates is turned ON so that a data bit cell group in/from which data is written and read out is selected. Accordingly, stored data can be rewritten multiple times by sequentially blowing the fuses in the cell group specifying circuit.
摘要翻译： 从解码器输出的选择信号根据单元组指定电路中的位单元中的状态（发生或不发生）或熔丝选择性地设置为高。 然后，晶体管栅极中的一个导通，从而选择写入/读出数据的数据位单元组。 因此，可以通过在单元组指定电路中顺序吹送保险丝来重写多个存储的数据。
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公开(公告)号：US07057956B2
公开(公告)日：2006-06-06
申请号：US10928366
申请日：2004-08-30
IPC分类号： G11C7/00
CPC分类号： G11C7/1096 , G11C7/062 , G11C7/1078
摘要： A semiconductor integrated circuit device includes: first and second nonvolatile memory elements; a first amplifier for amplifying an output signal from the first nonvolatile memory element to output the amplified signal; and a second amplifier for outputting to the first amplifier a control signal generated by amplifying an output signal from the second nonvolatile memory element. The second amplifier fixes the output signal from the first amplifier at a high potential or a low potential based on data stored in the second nonvolatile memory element.
摘要翻译： 一种半导体集成电路器件，包括：第一和第二非易失性存储元件; 第一放大器，用于放大来自第一非易失性存储器元件的输出信号以输出放大的信号; 以及第二放大器，用于向第一放大器输出通过放大来自第二非易失性存储元件的输出信号而产生的控制信号。 第二放大器基于存储在第二非易失性存储器元件中的数据，将来自第一放大器的输出信号固定在高电位或低电位。
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6.发明申请公开(公告)号：US20060023538A1
公开(公告)日：2006-02-02
申请号：US11191963
申请日：2005-07-29
CPC分类号： G11C16/12
摘要： A semiconductor memory device includes: first and second bit cells for storing complementary data; a scan circuit for outputting a selected data signal; a bit-cell selector receiving the output of the scan circuit and selecting one of the bit cells; and a data write controlling circuit for controlling data writing. Write paths for all the bit cells for storing “0” are not selected and data is written only in a bit cell for storing “1”, so that write operation performed in steps is achieved.
摘要翻译： 半导体存储器件包括：用于存储互补数据的第一和第二位单元; 用于输出所选数据信号的扫描电路; 接收所述扫描电路的输出并选择所述位单元之一的位单元选择器; 以及用于控制数据写入的数据写入控制电路。 用于存储“0”的所有位单元的写入路径不被选择，并且数据仅被写入用于存储“1”的位单元中，从而实现了步骤执行的写入操作。
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7.发明授权公开(公告)号：US07184304B2
公开(公告)日：2007-02-27
申请号：US11191963
申请日：2005-07-29
IPC分类号： G11C16/04
CPC分类号： G11C16/12
摘要： A semiconductor memory device includes: first and second bit cells for storing complementary data; a scan circuit for outputting a selected data signal; a bit-cell selector receiving the output of the scan circuit and selecting one of the bit cells; and a data write controlling circuit for controlling data writing. Write paths for all the bit cells for storing “0” are not selected and data is written only in a bit cell for storing “1”, so that write operation performed in steps is achieved.
摘要翻译： 半导体存储器件包括：用于存储互补数据的第一和第二位单元; 用于输出所选数据信号的扫描电路; 接收所述扫描电路的输出并选择所述位单元之一的位单元选择器; 以及用于控制数据写入的数据写入控制电路。 用于存储“0”的所有位单元的写入路径不被选择，并且数据仅被写入用于存储“1”的位单元中，从而实现了步骤执行的写入操作。
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公开(公告)号：US20060083046A1
公开(公告)日：2006-04-20
申请号：US11245075
申请日：2005-10-07
IPC分类号： G11C17/00
CPC分类号： G11C17/18
摘要： A fuse device and a program transistor are connected in series with each other. A flip-flop turns ON, in response to a start signal, the program transistor to start program of the fuse device. A 2-input NAND circuit outputs an end signal at a time point where change in a resistance value of the fuse device is increased to reach a predetermined level while monitoring change in the resistance value of the fuse device through change in a voltage at a junction point of the fuse device and the program transistor. The flip-flop turns OFF, in response to the end signal, the program transistor to automatically terminate the program of the fuse device. Thus, the resistance value of the fuse device is increased to the predetermined level in a minimum program time.
摘要翻译： 熔丝器件和程序晶体管彼此串联连接。 触发器响应于启动信号而导通，程序晶体管开始保险丝装置的编程。 2输入NAND电路在熔断器件的电阻值的变化增加以达到预定值的时间点输出结束信号，同时通过接点处的电压变化来监测熔丝器件的电阻值的变化 保险丝装置和程序晶体管的点。 触发器关闭，响应于结束信号，程序晶体管自动终止保险丝装置的程序。 因此，保险丝装置的电阻值在最小程序时间内增加到预定电平。
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公开(公告)号：US07002865B2
公开(公告)日：2006-02-21
申请号：US10935278
申请日：2004-09-08
IPC分类号： G11C7/02
CPC分类号： G11C16/0425
摘要： A nonvolatile semiconductor memory device includes: a first bit cell including a first MOS transistor whose source and drain are connected to form a first control gate and a second MOS transistor which has a floating gate in common with the first MOS transistor; a second bit cell including a third MOS transistor whose source and drain are connected to form a second control gate and a fourth MOS transistor which has a floating gate in common with the third MOS transistor; and a differential amplifier which receives input signals from drains of the respective second and fourth MOS transistors.
摘要翻译： 非易失性半导体存储器件包括：第一位单元，包括其源极和漏极连接以形成第一控制栅极的第一MOS晶体管和具有与第一MOS晶体管共同的浮动栅极的第二MOS晶体管; 第二位单元，包括其源极和漏极连接以形成第二控制栅极的第三MOS晶体管和具有与第三MOS晶体管共同的浮置栅极的第四MOS晶体管; 以及差分放大器，其从相应的第二和第四MOS晶体管的漏极接收输入信号。
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公开(公告)号：US20050162954A1
公开(公告)日：2005-07-28
申请号：US11038025
申请日：2005-01-21
IPC分类号： G11C7/02 , G11C11/409 , G11C11/419 , G11C29/00 , G11C29/50 , H01L27/105
CPC分类号： G11C29/50 , G11C2029/1204 , G11C2029/5004
摘要： In a normal operation, an output of a differential amplifier for amplifying a difference between first and second bit cells is output as readout data. In a test mode, when a first control signal is set to be “H”, the output of the differential amplifier is fixed to be “H” and thus an output of the first bit cell is read out through gates.
摘要翻译： 在正常操作中，输出用于放大第一和第二位单元之间的差分的差分放大器的输出作为读出数据。 在测试模式中，当第一控制信号被设置为“H”时，差分放大器的输出被固定为“H”，从而通过门读出第一位单元的输出。
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