公开(公告)号：US06226223B1

公开(公告)日：2001-05-01

申请号：US09511901

申请日：2000-02-23

申请人： Masanori Shirahama ,  Tsutomu Fujita ,  Masashi Agata ,  Kazunari Takahashi ,  Naoki Kuroda

发明人： Masanori Shirahama ,  Tsutomu Fujita ,  Masashi Agata ,  Kazunari Takahashi ,  Naoki Kuroda

IPC分类号： G11C800

CPC分类号： G11C7/222 ,  G11C7/22 ,  G11C11/24 ,  G11C11/4076

摘要： In a semiconductor memory device with multiple memory cells, each including a charge storage device and two transfer devices for transferring its charge, these memory cells are accessible with no select signal provided externally. The memory device includes a clock generator for generating first and second mutually complementary clock signals. In response to the first and second clock signals, one of first word lines and one of second word lines are activated alternately. Specifically, the first clock signal makes a memory cell accessible through a first bit line by activating the first word line and first transistor, while the second clock signal makes the memory cell accessible through a second bit line by activating the second word line and second transistor.

摘要翻译： 在具有多个存储器单元的半导体存储器件中，每个存储单元包括一个电荷存储器件和两个用于传送其电荷的转移器件，这些存储器单元是可以被访问的，没有从外部提供的选择信号。 存储器件包括用于产生第一和第二互补时钟信号的时钟发生器。 响应于第一和第二时钟信号，交替地激活第一字线和第二字线之一中的一个。 具体地，第一时钟信号通过激活第一字线和第一晶体管使得可通过第一位线访问存储单元，而第二时钟信号通过激活第二字线和第二晶体管使存储单元通过第二位线访问 。

公开(公告)号：US06181620B2

公开(公告)日：2001-01-30

申请号：US09484023

申请日：2000-01-18

申请人： Masashi Agata ,  Kazunari Takahashi ,  Tsutomu Fujita ,  Naoki Kuroda ,  Toshio Yamada

发明人： Masashi Agata ,  Kazunari Takahashi ,  Tsutomu Fujita ,  Naoki Kuroda ,  Toshio Yamada

IPC分类号： G11C1124

CPC分类号： G11C11/405 ,  G11C7/1042 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4091 ,  G11C11/4094

摘要： The semiconductor storage device of this invention includes memory cells each having two transistors and one storage capacitor. Each memory cell is connected with a first word line and a first bit line for a first port and a second word line and a second bit line for a second port. The first and second bit lines are alternately disposed in an open bit line configuration. In the operation of the semiconductor storage device, in a period when a first precharge signal for precharging each first bit line or a first sense amplifier activating signal for activating a first sense amplifier is kept in an active state, a second precharge signal for precharging each second bit line and a second sense amplifier activating signal for activating a second sense amplifier are both placed in an inactive state.

摘要翻译： 本发明的半导体存储装置包括具有两个晶体管和一个存储电容器的存储单元。 每个存储单元与第一字线和用于第一端口的第一位线和用于第二端口的第二字线和第二位线连接。 第一位线和第二位线以开放位线配置交替布置。 在半导体存储装置的动作中，在对第一读出放大器的第一预定电荷进行预充电的第一预充电信号或激活第一读出放大器的第一读出放大器的激活信号保持为有效状态的期间内， 第二位线和用于激活第二读出放大器的第二读出放大器激活信号都处于非活动状态。

公开(公告)号：US06169684A

公开(公告)日：2001-01-02

申请号：US09495473

申请日：2000-02-01

申请人： Kazunari Takahashi ,  Masashi Agata ,  Naoki Kuroda ,  Tsutomu Fujita

发明人： Kazunari Takahashi ,  Masashi Agata ,  Naoki Kuroda ,  Tsutomu Fujita

IPC分类号： G11C1500

CPC分类号： G11C11/4097 ,  G06F12/0893 ,  G06F2212/3042 ,  G11C11/005

摘要： A cache memory including a first memory array and a main memory including a second memory array are integrated together on the same semiconductor substrate. Each memory cell in the first memory array is of a 2Tr1C type including: first and second transistors, the sources of which are connected together; and a data storage capacitor, one of the two electrodes of which is connected to the common source of the first and second transistors. Each memory cell in the second memory array is of a 1Tr1C type including: a third transistor; and a data storage capacitor, one of the two electrodes of which is connected to the source of the third transistor.

摘要翻译： 包括第一存储器阵列和包括第二存储器阵列的主存储器的高速缓存存储器集成在同一半导体衬底上。 第一存储器阵列中的每个存储单元是2Tr1C类型，包括：第一和第二晶体管，其源极连接在一起; 以及数据存储电容器，其两个电极中的一个连接到第一和第二晶体管的公共源。 第二存储器阵列中的每个存储单元是1Tr1C类型，包括：第三晶体管; 以及数据存储电容器，其两个电极中的一个连接到第三晶体管的源极。

公开(公告)号：US06788565B2

公开(公告)日：2004-09-07

申请号：US10394262

申请日：2003-03-24

申请人： Masashi Agata ,  Kazunari Takahashi ,  Masanori Shirahama ,  Naoki Kuroda ,  Hiroyuki Sadakata ,  Ryuji Nishihara

发明人： Masashi Agata ,  Kazunari Takahashi ,  Masanori Shirahama ,  Naoki Kuroda ,  Hiroyuki Sadakata ,  Ryuji Nishihara

IPC分类号： G11C1140

CPC分类号： G11C11/405 ,  H01L27/108

摘要： A semiconductor memory device has a plurality of memory cells each having a first transistor, a second transistor having a source or drain connected to one portion of the source or drain of the first transistor, and a third transistor having a source or drain connected to the other portion of the source or drain of the first transistor. The first transistor accumulates, in the channel thereof, charges transferred from the second and third transistors.

摘要翻译： 半导体存储器件具有多个存储单元，每个存储单元具有第一晶体管，第二晶体管具有连接到第一晶体管的源极或漏极的一部分的源极或漏极;以及第三晶体管，源极或漏极连接到第一晶体管， 第一晶体管的源极或漏极的另一部分。 第一晶体管在其通道中累积从第二和第三晶体管传送的电荷。

公开(公告)号：US6137713A

公开(公告)日：2000-10-24

申请号：US420576

申请日：1999-10-19

申请人： Naoki Kuroda ,  Masashi Agata ,  Kazunari Takahashi

发明人： Naoki Kuroda ,  Masashi Agata ,  Kazunari Takahashi

IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C11/24 ,  G11C11/405 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/108 ,  G11C11/24 ,  G11C11/405 ,  G11C5/02 ,  G11C5/063 ,  H01L27/10885

摘要： Over an active region with two bent portions on a semiconductor substrate, first and second word lines extend to cross these bent portions and to be vertically spaced apart from each other. Around at the center of the active region, a capacitor for storing data thereon and a capacitor contact are formed. A first bit line contact, which is connected to the active region, is formed on the opposite side to the capacitor contact across the first word line over the active region. A second bit line contact, which is also connected to the active region, is formed on the opposite side to the capacitor contact across the second word line over the active region. These first and second bit line contacts are provided substantially symmetrically about the center of the memory cell. In a pair of memory cells adjacent to each other along bit lines, one vertical end of the active region in one of the memory cells is continuous with an associated vertical end of the active region in the other memory cell. And each of the first and second bit line contacts is shared between an adjacent pair of memory cells.

摘要翻译： 在半导体衬底上具有两个弯曲部分的有源区域上，第一和第二字线延伸以跨越这些弯曲部分并且彼此垂直间隔开。 在有源区域的中心附近形成用于存储数据的电容器和电容器触点。 连接到有源区域的第一位线触点形成在跨过有源区域的跨第一字线的电容器触点的相反侧。 还连接到有源区的第二位线触点形成在跨过有源区的跨越第二字线的电容器触点的相反侧。 这些第一和第二位线触点基本上围绕存储器单元的中心对称地设置。 在沿着位线彼此相邻的一对存储单元中，一个存储单元中的有源区的一个垂直端与另一个存储单元中的有源区的相关联的垂直端连续。 并且第一和第二位线触点中的每一个在相邻的一对存储单元之间共享。

公开(公告)号：US06862205B2

公开(公告)日：2005-03-01

申请号：US10372971

申请日：2003-02-26

申请人： Masashi Agata ,  Kazunari Takahashi

发明人： Masashi Agata ,  Kazunari Takahashi

IPC分类号： G11C11/403 ,  G11C8/18 ,  G11C11/405 ,  G11C11/406 ,  G11C11/408 ,  G11C11/24 ,  G11C7/00 ,  G11C7/02 ,  G11C8/00 ,  G11C11/34

CPC分类号： G11C8/18 ,  G11C11/405 ,  G11C11/406 ,  G11C11/4085

摘要： The semiconductor memory device includes: a memory cell including a capacitor having a charge storage node and a first MIS transistor and a second MIS transistor each having a source connected to the charge storage node; a first word line and a first bit line respectively connected to the gate and the drain of the first MIS transistor; a second word line and a second bit line respectively connected to the gate and the drain of the second MIS transistor; and a timer circuit for generating a periodic signal having a predetermined period. The first word line or the second word line is activated in response to the periodic signal.

摘要翻译： 半导体存储器件包括：存储单元，其包括具有电荷存储节点的电容器和第一MIS晶体管和第二MIS晶体管，每个MIS晶体管的源极连接到电荷存储节点; 分别连接到第一MIS晶体管的栅极和漏极的第一字线和第一位线; 分别连接到第二MIS晶体管的栅极和漏极的第二字线和第二位线; 以及用于产生具有预定周期的周期信号的定时器电路。 第一字线或第二字线响应于周期性信号被激活。

公开(公告)号：US08920330B2

公开(公告)日：2014-12-30

申请号：US12662491

申请日：2010-04-20

申请人： Takashi Nakanishi ,  Kazunari Takahashi ,  Kenichi Matsumoto

发明人： Takashi Nakanishi ,  Kazunari Takahashi ,  Kenichi Matsumoto

IPC分类号： A61B5/02 ,  A61B5/022 ,  A61B5/00

CPC分类号： A61B5/02233 ,  A61B5/6824

摘要： A body compressor 1 is provided with a fluid bag 2, a band-like body 3 and a metal clip 4, wherein a fixed part 42 of the metal clip 4 is attached such that it is positioned above the outer surface of a skin pinching prevention tag part 5, and the skin pinching prevention tag part 5 has a reinforcing member 6 which allows the bending rigidity of a center-side part 51 and an intermediate part 52 to be higher than that of a front-side part 53.

摘要翻译： 本体压缩机1设置有流体袋2，带状体3和金属夹4，其中金属夹4的固定部42被安装成使其位于皮肤防止夹紧的外表面上方 标签部分5，并且防绷带标签部分5具有允许中心侧部分51和中间部分52的弯曲刚度高于前侧部分53的弯曲刚度的加强部件6。

公开(公告)号：US20140049045A1

公开(公告)日：2014-02-20

申请号：US14006245

申请日：2012-02-24

申请人： Masaki Yoshikawa ,  Takuya Nagahama ,  Hiroshi Chikatsune ,  Jun Takano ,  Takamasa Kawai ,  Kazunari Takahashi ,  Masateru Ueta ,  Osamu Sonobe

发明人： Masaki Yoshikawa ,  Takuya Nagahama ,  Hiroshi Chikatsune ,  Jun Takano ,  Takamasa Kawai ,  Kazunari Takahashi ,  Masateru Ueta ,  Osamu Sonobe

IPC分类号： F16L15/00

CPC分类号： F16L15/001 ,  E21B17/042 ,  F16L15/004 ,  F16L15/06

摘要： Provided is a threaded joint for steel pipes having high sealability even under a bending load. In the threaded joint, when a pin 3 and a box 1 are threadedly connected with each other, the outer peripheral face of a nose 8 of the pin and the inner peripheral face of a nose of the box are in metal-to-metal contact with each other at a contact portion and the contact portion serves as a seal portion 20. A threaded portion, at which the externally threaded portion 7 and the internally threaded portion 5 are threadedly connected with each other, has a negative load flank angle α, shoulder portions 12 and 14 have a negative torque shoulder angle β, and the ratio L/d0 of a length L of the nose and a pipe outside diameter d0 is equal to or higher than 0.08.

摘要翻译： 即使在弯曲载荷下也具有高密封性的钢管用螺纹接头。 在螺纹接头中，当销3和盒1彼此螺纹连接时，销的鼻部8的外周面和箱的鼻部的内周面与金属对金属接触 彼此在接触部分处，并且接触部分用作密封部分20.外螺纹部分7和内螺纹部分5彼此螺纹连接的螺纹部分具有负的负载侧角α， 肩部12和14具有负扭矩肩角β，并且鼻部长度L和管外径d0的比L / d0等于或高于0.08。

公开(公告)号：US20130181442A1

公开(公告)日：2013-07-18

申请号：US13807883

申请日：2011-06-22

申请人： Osamu Sonobe ,  Takuya Nagahama ,  Masaki Yoshikawa ,  Jun Takano ,  Takamasa Kawai ,  Kazunari Takahashi

发明人： Osamu Sonobe ,  Takuya Nagahama ,  Masaki Yoshikawa ,  Jun Takano ,  Takamasa Kawai ,  Kazunari Takahashi

IPC分类号： E21B17/042 ,  F16L15/00

CPC分类号： E21B17/042 ,  F16L15/00 ,  F16L15/004 ,  F16L15/06

摘要： Provided is a threaded joint for a pipe in which scalability, compression resistance, and galling resistance are enhanced. Specifically, a pin nose outer peripheral surface forms an outward convex curve in an axial cross-sectional view; the convex curve is such that a composite R curve, in which a plurality of outward convex arcs having different radiuses of curvature are connected in sequence to a generating line of a cylindrical portion next to a male member, is curved such that the radiuses of curvature increase with distance from the male member and tangents on connection points of the arcs are aligned with those of corresponding arcs connected thereto; and the inner peripheral surface of a box component facing the pin nose is a tapered surface that interferes with the pin nose outer peripheral surface when connected to a pin component.

摘要翻译： 提供了一种用于管道的螺纹接头，其中可扩展性，抗压缩性和耐磨损性提高。 具体地，针鼻外周面在轴向剖视图中形成向外的凸曲线; 凸曲线使得其中具有不同的曲率半径的多个向外凸起的弧线与邻近阳构件的圆柱形部分的生成线连续地连接的复合R曲线弯曲成使得曲率半径 随着与阳构件的距离增加并且在圆弧的连接点上的切线与与其连接的相应弧的弧线对准; 并且面向销头的箱体部件的内周面是与销部件连接时与销头外周面相干涉的锥形面。

公开(公告)号：US06463006B2

公开(公告)日：2002-10-08

申请号：US09902605

申请日：2001-07-12

申请人： Takeshi Nakano ,  Kazunari Takahashi

发明人： Takeshi Nakano ,  Kazunari Takahashi

IPC分类号： G11C800

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/22 ,  G11C7/222

摘要： A semiconductor integrated circuit is disclosed which includes a clock synchronous memory, an internal clock generating circuit, a clock selecting circuit, a data output converting circuit, and a data output selecting circuit. The clock synchronous memory is disposed to receive a control signal, an address signal, and a data input and provide an internal data output. The internal clock generating circuit is disposed to generate an internal clock signal having a frequency higher than that of an external clock signal. The clock selecting circuit is disposed to select between the external clock signal and the internal clock signal and send the selected clock signal to the clock synchronous memory. The data output converting circuit is disposed to convert the internal data output into an external data output in synchronization with a clock signal having a frequency lower than that of the internal clock signal. The data output selecting circuit is disposed to select between the internal data output and the external data output and provide the selected data output.

摘要翻译： 公开了一种半导体集成电路，其包括时钟同步存储器，内部时钟发生电路，时钟选择电路，数据输出转换电路和数据输出选择电路。 时钟同步存储器被设置为接收控制信号，地址信号和数据输入并提供内部数据输出。 内部时钟发生电路被设置为产生具有高于外部时钟信号的频率的内部时钟信号。 时钟选择电路被设置为在外部时钟信号和内部时钟信号之间进行选择，并将选择的时钟信号发送到时钟同步存储器。 数据输出转换电路被设置成与具有低于内部时钟信号的频率的时钟信号同步地将内部数据输出转换成外部数据输出。 数据输出选择电路被设置为在内部数据输出和外部数据输出之间进行选择，并提供所选择的数据输出。