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公开(公告)号：US06226223B1
公开(公告)日：2001-05-01
申请号：US09511901
申请日：2000-02-23
IPC分类号： G11C800
CPC分类号： G11C7/222 , G11C7/22 , G11C11/24 , G11C11/4076
摘要： In a semiconductor memory device with multiple memory cells, each including a charge storage device and two transfer devices for transferring its charge, these memory cells are accessible with no select signal provided externally. The memory device includes a clock generator for generating first and second mutually complementary clock signals. In response to the first and second clock signals, one of first word lines and one of second word lines are activated alternately. Specifically, the first clock signal makes a memory cell accessible through a first bit line by activating the first word line and first transistor, while the second clock signal makes the memory cell accessible through a second bit line by activating the second word line and second transistor.
摘要翻译： 在具有多个存储器单元的半导体存储器件中，每个存储单元包括一个电荷存储器件和两个用于传送其电荷的转移器件，这些存储器单元是可以被访问的，没有从外部提供的选择信号。 存储器件包括用于产生第一和第二互补时钟信号的时钟发生器。 响应于第一和第二时钟信号，交替地激活第一字线和第二字线之一中的一个。 具体地，第一时钟信号通过激活第一字线和第一晶体管使得可通过第一位线访问存储单元，而第二时钟信号通过激活第二字线和第二晶体管使存储单元通过第二位线访问 。
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公开(公告)号：US06788565B2
公开(公告)日：2004-09-07
申请号：US10394262
申请日：2003-03-24
申请人： Masashi Agata , Kazunari Takahashi , Masanori Shirahama , Naoki Kuroda , Hiroyuki Sadakata , Ryuji Nishihara
发明人： Masashi Agata , Kazunari Takahashi , Masanori Shirahama , Naoki Kuroda , Hiroyuki Sadakata , Ryuji Nishihara
IPC分类号： G11C1140
CPC分类号： G11C11/405 , H01L27/108
摘要： A semiconductor memory device has a plurality of memory cells each having a first transistor, a second transistor having a source or drain connected to one portion of the source or drain of the first transistor, and a third transistor having a source or drain connected to the other portion of the source or drain of the first transistor. The first transistor accumulates, in the channel thereof, charges transferred from the second and third transistors.
摘要翻译： 半导体存储器件具有多个存储单元，每个存储单元具有第一晶体管，第二晶体管具有连接到第一晶体管的源极或漏极的一部分的源极或漏极;以及第三晶体管，源极或漏极连接到第一晶体管， 第一晶体管的源极或漏极的另一部分。 第一晶体管在其通道中累积从第二和第三晶体管传送的电荷。
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公开(公告)号：US06181620B2
公开(公告)日：2001-01-30
申请号：US09484023
申请日：2000-01-18
IPC分类号： G11C1124
CPC分类号： G11C11/405 , G11C7/1042 , G11C7/12 , G11C7/22 , G11C11/4091 , G11C11/4094
摘要： The semiconductor storage device of this invention includes memory cells each having two transistors and one storage capacitor. Each memory cell is connected with a first word line and a first bit line for a first port and a second word line and a second bit line for a second port. The first and second bit lines are alternately disposed in an open bit line configuration. In the operation of the semiconductor storage device, in a period when a first precharge signal for precharging each first bit line or a first sense amplifier activating signal for activating a first sense amplifier is kept in an active state, a second precharge signal for precharging each second bit line and a second sense amplifier activating signal for activating a second sense amplifier are both placed in an inactive state.
摘要翻译： 本发明的半导体存储装置包括具有两个晶体管和一个存储电容器的存储单元。 每个存储单元与第一字线和用于第一端口的第一位线和用于第二端口的第二字线和第二位线连接。 第一位线和第二位线以开放位线配置交替布置。 在半导体存储装置的动作中，在对第一读出放大器的第一预定电荷进行预充电的第一预充电信号或激活第一读出放大器的第一读出放大器的激活信号保持为有效状态的期间内， 第二位线和用于激活第二读出放大器的第二读出放大器激活信号都处于非活动状态。
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公开(公告)号：US06169684A
公开(公告)日：2001-01-02
申请号：US09495473
申请日：2000-02-01
IPC分类号： G11C1500
CPC分类号： G11C11/4097 , G06F12/0893 , G06F2212/3042 , G11C11/005
摘要： A cache memory including a first memory array and a main memory including a second memory array are integrated together on the same semiconductor substrate. Each memory cell in the first memory array is of a 2Tr1C type including: first and second transistors, the sources of which are connected together; and a data storage capacitor, one of the two electrodes of which is connected to the common source of the first and second transistors. Each memory cell in the second memory array is of a 1Tr1C type including: a third transistor; and a data storage capacitor, one of the two electrodes of which is connected to the source of the third transistor.
摘要翻译： 包括第一存储器阵列和包括第二存储器阵列的主存储器的高速缓存存储器集成在同一半导体衬底上。 第一存储器阵列中的每个存储单元是2Tr1C类型，包括：第一和第二晶体管，其源极连接在一起; 以及数据存储电容器，其两个电极中的一个连接到第一和第二晶体管的公共源。 第二存储器阵列中的每个存储单元是1Tr1C类型，包括：第三晶体管; 以及数据存储电容器，其两个电极中的一个连接到第三晶体管的源极。
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公开(公告)号：US6137713A
公开(公告)日：2000-10-24
申请号：US420576
申请日：1999-10-19
申请人： Naoki Kuroda , Masashi Agata , Kazunari Takahashi
发明人： Naoki Kuroda , Masashi Agata , Kazunari Takahashi
IPC分类号： G11C5/02 , G11C5/06 , G11C11/24 , G11C11/405 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/108 , G11C11/24 , G11C11/405 , G11C5/02 , G11C5/063 , H01L27/10885
摘要： Over an active region with two bent portions on a semiconductor substrate, first and second word lines extend to cross these bent portions and to be vertically spaced apart from each other. Around at the center of the active region, a capacitor for storing data thereon and a capacitor contact are formed. A first bit line contact, which is connected to the active region, is formed on the opposite side to the capacitor contact across the first word line over the active region. A second bit line contact, which is also connected to the active region, is formed on the opposite side to the capacitor contact across the second word line over the active region. These first and second bit line contacts are provided substantially symmetrically about the center of the memory cell. In a pair of memory cells adjacent to each other along bit lines, one vertical end of the active region in one of the memory cells is continuous with an associated vertical end of the active region in the other memory cell. And each of the first and second bit line contacts is shared between an adjacent pair of memory cells.
摘要翻译： 在半导体衬底上具有两个弯曲部分的有源区域上，第一和第二字线延伸以跨越这些弯曲部分并且彼此垂直间隔开。 在有源区域的中心附近形成用于存储数据的电容器和电容器触点。 连接到有源区域的第一位线触点形成在跨过有源区域的跨第一字线的电容器触点的相反侧。 还连接到有源区的第二位线触点形成在跨过有源区的跨越第二字线的电容器触点的相反侧。 这些第一和第二位线触点基本上围绕存储器单元的中心对称地设置。 在沿着位线彼此相邻的一对存储单元中，一个存储单元中的有源区的一个垂直端与另一个存储单元中的有源区的相关联的垂直端连续。 并且第一和第二位线触点中的每一个在相邻的一对存储单元之间共享。
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公开(公告)号：US20060083046A1
公开(公告)日：2006-04-20
申请号：US11245075
申请日：2005-10-07
IPC分类号： G11C17/00
CPC分类号： G11C17/18
摘要： A fuse device and a program transistor are connected in series with each other. A flip-flop turns ON, in response to a start signal, the program transistor to start program of the fuse device. A 2-input NAND circuit outputs an end signal at a time point where change in a resistance value of the fuse device is increased to reach a predetermined level while monitoring change in the resistance value of the fuse device through change in a voltage at a junction point of the fuse device and the program transistor. The flip-flop turns OFF, in response to the end signal, the program transistor to automatically terminate the program of the fuse device. Thus, the resistance value of the fuse device is increased to the predetermined level in a minimum program time.
摘要翻译： 熔丝器件和程序晶体管彼此串联连接。 触发器响应于启动信号而导通，程序晶体管开始保险丝装置的编程。 2输入NAND电路在熔断器件的电阻值的变化增加以达到预定值的时间点输出结束信号，同时通过接点处的电压变化来监测熔丝器件的电阻值的变化 保险丝装置和程序晶体管的点。 触发器关闭，响应于结束信号，程序晶体管自动终止保险丝装置的程序。 因此，保险丝装置的电阻值在最小程序时间内增加到预定电平。
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公开(公告)号：US07002865B2
公开(公告)日：2006-02-21
申请号：US10935278
申请日：2004-09-08
IPC分类号： G11C7/02
CPC分类号： G11C16/0425
摘要： A nonvolatile semiconductor memory device includes: a first bit cell including a first MOS transistor whose source and drain are connected to form a first control gate and a second MOS transistor which has a floating gate in common with the first MOS transistor; a second bit cell including a third MOS transistor whose source and drain are connected to form a second control gate and a fourth MOS transistor which has a floating gate in common with the third MOS transistor; and a differential amplifier which receives input signals from drains of the respective second and fourth MOS transistors.
摘要翻译： 非易失性半导体存储器件包括：第一位单元，包括其源极和漏极连接以形成第一控制栅极的第一MOS晶体管和具有与第一MOS晶体管共同的浮动栅极的第二MOS晶体管; 第二位单元，包括其源极和漏极连接以形成第二控制栅极的第三MOS晶体管和具有与第三MOS晶体管共同的浮置栅极的第四MOS晶体管; 以及差分放大器，其从相应的第二和第四MOS晶体管的漏极接收输入信号。
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公开(公告)号：US20050162954A1
公开(公告)日：2005-07-28
申请号：US11038025
申请日：2005-01-21
IPC分类号： G11C7/02 , G11C11/409 , G11C11/419 , G11C29/00 , G11C29/50 , H01L27/105
CPC分类号： G11C29/50 , G11C2029/1204 , G11C2029/5004
摘要： In a normal operation, an output of a differential amplifier for amplifying a difference between first and second bit cells is output as readout data. In a test mode, when a first control signal is set to be “H”, the output of the differential amplifier is fixed to be “H” and thus an output of the first bit cell is read out through gates.
摘要翻译： 在正常操作中，输出用于放大第一和第二位单元之间的差分的差分放大器的输出作为读出数据。 在测试模式中，当第一控制信号被设置为“H”时，差分放大器的输出被固定为“H”，从而通过门读出第一位单元的输出。
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公开(公告)号：US20050047236A1
公开(公告)日：2005-03-03
申请号：US10928366
申请日：2004-08-30
CPC分类号： G11C7/1096 , G11C7/062 , G11C7/1078
摘要： A semiconductor integrated circuit device includes: first and second nonvolatile memory elements; a first amplifier for amplifying an output signal from the first nonvolatile memory element to output the amplified signal; and a second amplifier for outputting to the first amplifier a control signal generated by amplifying an output signal from the second nonvolatile memory element. The second amplifier fixes the output signal from the first amplifier at a high potential or a low potential based on data stored in the second nonvolatile memory element.
摘要翻译： 一种半导体集成电路器件，包括：第一和第二非易失性存储元件; 第一放大器，用于放大来自第一非易失性存储器元件的输出信号以输出放大的信号; 以及第二放大器，用于向第一放大器输出通过放大来自第二非易失性存储元件的输出信号而产生的控制信号。 第二放大器基于存储在第二非易失性存储器元件中的数据，将来自第一放大器的输出信号固定在高电位或低电位。
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公开(公告)号：US07203117B2
公开(公告)日：2007-04-10
申请号：US11245075
申请日：2005-10-07
IPC分类号： G11C17/18
CPC分类号： G11C17/18
摘要： A fuse device and a program transistor are connected in series with each other. A flip-flop turns ON, in response to a start signal, the program transistor to start program of the fuse device. A 2-input NAND circuit outputs an end signal at a time point where change in a resistance value of the fuse device is increased to reach a predetermined level while monitoring change in the resistance value of the fuse device through change in a voltage at a junction point of the fuse device and the program transistor. The flip-flop turns OFF, in response to the end signal, the program transistor to automatically terminate the program of the fuse device. Thus, the resistance value of the fuse device is increased to the predetermined level in a minimum program time.
摘要翻译： 熔丝器件和程序晶体管彼此串联连接。 触发器响应于启动信号而导通，程序晶体管开始保险丝装置的编程。 2输入NAND电路在熔断器件的电阻值的变化增加以达到预定值的时间点输出结束信号，同时通过接点处的电压变化来监测熔丝器件的电阻值的变化 保险丝装置和程序晶体管的点。 触发器关闭，响应于结束信号，程序晶体管自动终止保险丝装置的程序。 因此，保险丝装置的电阻值在最小程序时间内增加到预定电平。
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