公开(公告)号：US20200310521A1

公开(公告)日：2020-10-01

申请号：US16863968

申请日：2020-04-30

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh ,  Baekkyu Choi ,  Thomas H. Kinsley

IPC: G06F1/3225 ,  G06F1/3234 ,  G06F3/06

Abstract: Methods, systems, and devices for predictive power management are described. Correlations may be identified between a set of commands performed at the memory device and oscillating voltage patterns, or a resonance frequency, or both. Voltages may be monitored by the memory device and be compared to the identified voltage pattern to mitigate undesirable oscillating voltages and resonance frequency.

公开(公告)号：US20200251150A1

公开(公告)日：2020-08-06

申请号：US16268092

申请日：2019-02-05

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh ,  Thomas H. Kinsley ,  Baekkyu Choi

IPC: G11C5/06 ,  G11C11/22 ,  G11C11/4091 ,  G06F13/16

Abstract: Methods and devices for dynamic allocation of a capacitive component in a memory device are described. A memory device may include one or more voltage rails for distributing supply voltages to a memory die. A memory device may include a capacitive component that may be dynamically coupled to a voltage rail based on an identification of an operating condition on the memory die, such as a voltage droop on the voltage rail. The capacitive component may be dynamically coupled with the voltage rail to maintain the supply voltage on the voltage rail during periods of high demand. The capacitive component may be dynamically switched between voltage rails during operation of the memory device based on operating conditions associated with the voltage rails.

公开(公告)号：US11948661B2

公开(公告)日：2024-04-02

申请号：US17244942

申请日：2021-04-29

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  Dirgha Khatri ,  Elancheren Durai ,  Quincy R. Holton ,  Timothy M. Hollis ,  Matthew B. Leslie ,  Baekkyu Choi ,  Boe L Holbrook ,  Yogesh Sharma ,  Scott R. Cyr

IPC: G11C8/18 ,  G11C7/10 ,  G11C8/06 ,  G11C8/12

CPC classification number: G11C8/18 ,  G11C7/1096 ,  G11C8/06 ,  G11C8/12

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which clock trees can be separately optimized to provide a coarse alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal), and/or in which individual memory devices can be isolated for fine-tuning of device-specific alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal). Moreover, individual memory devices can be isolated for fine-tuning of device-specific equalization of a command/address signal (and/or a chip select signal or other control signal).

公开(公告)号：US11749357B2

公开(公告)日：2023-09-05

申请号：US18094698

申请日：2023-01-09

Applicant: Micron Technology, Inc.

Inventor： Baekkyu Choi ,  Fuad Badrieh ,  Thomas H. Kinsley

IPC: G11C5/14 ,  G11C16/30 ,  G06F1/28 ,  G06F1/3296

CPC classification number: G11C16/30 ,  G06F1/28 ,  G06F1/3296 ,  G11C5/14

Abstract: A memory device may include a pin for receiving a direct current (DC) voltage indicating an operating configuration setting of the memory device and for communicating an alternating current (AC) voltage signal that provides feedback to a power management component. The memory device may determine that a supply voltage is outside of a target range, and may drive the AC signal onto the pin based on determining that the supply voltage is outside the range. The pin may be coupled with a capacitive component the passes the AC signal and blocks the DC signal. The power management component may receive the capacitively coupled AC signal and may maintain or adjust the supply voltage based on the received AC signal.

公开(公告)号：US11721386B2

公开(公告)日：2023-08-08

申请号：US17470743

申请日：2021-09-09

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh ,  Thomas H. Kinsley ,  Baekkyu Choi

IPC: G11C11/4074

CPC classification number: G11C11/4074

Abstract: Techniques, apparatus, and devices for managing power in a memory die are described. A memory die may include an array of memory cells and one or more voltage sensors. Each voltage sensor may be on the same substrate as the array of memory cells and may sense a voltage at a location associated with the array. The voltage sensors may generate one or more analog voltage signals that may be converted to one or more digital signals on the memory die. In some cases, the analog voltage signals may be converted to digital signals using an oscillator and a counter on the memory die. The digital signal may be provided to a power management integrated circuit (PMIC), which may adjust a voltage supplied to the array based on the digital signal.

公开(公告)号：US11677537B2

公开(公告)日：2023-06-13

申请号：US17204681

申请日：2021-03-17

Applicant: Micron Technology, Inc.

Inventor： Hyunui Lee ,  Won Joo Yun ,  Baekkyu Choi

IPC: H04L7/00 ,  H04L25/00 ,  H04L25/40 ,  H04L7/02

CPC classification number: H04L7/02

Abstract: The present application is directed to signal delay control and related apparatuses, systems, and methods. An apparatus includes delay elements and control circuitry electrically connected to the delay elements. The delay elements are configured to receive skewed data signals and delay codes indicating delay quantities. The delay elements are also configured to provide delayed data signals delayed relative to the skewed data signals by the delay quantities. The control circuitry is configured to provide the delay codes, which are selected to reduce a timing skew of the delayed data signals relative to a timing skew of the skewed data signals. A system includes a first device, a second device including the apparatus, and transmission lines electrically connected between the first device and the second device. A method includes calibrating the delay codes.

公开(公告)号：US20230162802A1

公开(公告)日：2023-05-25

申请号：US18094698

申请日：2023-01-09

Applicant: Micron Technology, Inc.

Inventor： Baekkyu Choi ,  Fuad Badrieh ,  Thomas H. Kinsley

IPC: G11C16/30 ,  G06F1/28 ,  G06F1/3296

CPC classification number: G11C16/30 ,  G06F1/28 ,  G06F1/3296 ,  G11C5/14

Abstract: A memory device may include a pin for receiving a direct current (DC) voltage indicating an operating configuration setting of the memory device and for communicating an alternating current (AC) voltage signal that provides feedback to a power management component. The memory device may determine that a supply voltage is outside of a target range, and may drive the AC signal onto the pin based on determining that the supply voltage is outside the range. The pin may be coupled with a capacitive component the passes the AC signal and blocks the DC signal. The power management component may receive the capacitively coupled AC signal and may maintain or adjust the supply voltage based on the received AC signal.

公开(公告)号：US11568915B2

公开(公告)日：2023-01-31

申请号：US17315711

申请日：2021-05-10

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh ,  Thomas H. Kinsley ,  Baekkyu Choi

IPC: G11C11/4074 ,  G11C11/22

Abstract: Methods, systems, and devices for voltage adjustment of memory dies based on weighted feedback are described. A supply voltage may be measured at various areas of a memory die, weights may be applied to the measured voltages based on the area from which the particular voltage was measured. The supply voltage may be adjusted based on the weighted signals. The signals may be weighted using digital or analog techniques. Different durations of time in which oscillations from an oscillator circuit are counted may provide weighting for a signal. Weights applied to the signals may be dynamically adjusted, which may allow the weights to be tuned or changed based on changes to operating conditions of the memory dies.

公开(公告)号：US20230005551A1

公开(公告)日：2023-01-05

申请号：US17877697

申请日：2022-07-29

Applicant: Micron Technology, Inc.

Inventor： Baekkyu Choi ,  Fuad Badrieh ,  Thomas H. Kinsley

IPC: G11C16/30 ,  G11C5/14

Abstract: Methods, systems, and devices for power regulation for memory systems are described. In one example, a memory system, such as a memory module, may include a substrate, and an input/output component coupled with the substrate and operable to communicate signals with a host system. The memory system may also include one or more memory devices coupled with the substrate and the input/output component and operable to store data for the host system. A memory device of the one or more memory devices may include a power management component in its package with one or more memory dies. The power management component may be coupled with the one or more memory dies, and feedback component, and may be operable to provide one or more supply voltages for the one or more memory dies based on one or more voltages associated with the memory system.

公开(公告)号：US20220391002A1

公开(公告)日：2022-12-08

申请号：US17842517

申请日：2022-06-16

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh ,  Baekkyu Choi ,  Thomas H. Kinsley

IPC: G06F1/3225 ,  G06F1/3234 ,  G06F3/06

Abstract: Methods, systems, and devices for predictive power management are described. Correlations may be identified between a set of commands performed at the memory device and oscillating voltage patterns, or a resonance frequency, or both. Voltages may be monitored by the memory device and be compared to the identified voltage pattern to mitigate undesirable oscillating voltages and resonance frequency.