公开(公告)号：US11593005B2

公开(公告)日：2023-02-28

申请号：US17219489

申请日：2021-03-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Mustafa N Kaynak ,  Peter Feeley ,  Sampath K Ratnam ,  Shane Nowell ,  Sivagnanam Parthasarathy ,  Karl D Schuh ,  Jiangang Wu

IPC: G06F3/06 ,  G11C16/26

Abstract: A processing device of a memory sub-system is configured to sort a plurality of blocks of the memory device; divide the sorted plurality of blocks into a plurality of block segments; scan a first block at a first boundary of a first block segment of the plurality of block segments; scan a second block at a second boundary of the first block segment; identify, based on a scanning result of the first block, a first voltage bin associated with the first block; identify, based on a second scanning result of the second block, a second voltage bin associated with the second block; and responsive to determining that the first voltage bin matches the second voltage bin, assign the first voltage bin to each block of a subset of the plurality of blocks assigned to the first block segment.

公开(公告)号：US11437108B1

公开(公告)日：2022-09-06

申请号：US17230786

申请日：2021-04-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Karl Schuh ,  Mustafa N Kaynak ,  Xiangang Luo ,  Shane Nowell ,  Devin Batutis ,  Sivagnanam Parthasarathy ,  Sampath Ratnam ,  Jiangang Wu ,  Peter Feeley

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/10 ,  G11C7/04 ,  G11C16/32 ,  G11C16/26

Abstract: A difference between a current temperature and a prior temperature of a memory device is determined. In response to a determination that the difference between the current temperature and the prior temperature of the memory device satisfies a temperature criterion, an amount of voltage shift is measured for a set of memory cells of a block family associated with a first voltage bin of a set of voltage bins at the memory device. The first voltage bin is associated with a first voltage offset. An adjusted amount of voltage shift is determined for the set of memory cells based on the determined amount of voltage shift and a temporary voltage shift offset associated with the difference between the current temperature and the prior temperature for the memory device. In response to a determination that the adjusted amount of voltage shift satisfies a voltage shift criterion, the block family is associated with a second voltage bin of the set of voltage bins. The second voltage bin is associated with a second voltage offset.

公开(公告)号：US11410734B1

公开(公告)日：2022-08-09

申请号：US17219498

申请日：2021-03-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Sampath K Ratnam ,  Shane Nowell ,  Sivagnanam Parthasarathy ,  Mustafa N Kaynak ,  Karl D Schuh ,  Peter Feeley ,  Jiangang Wu

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/20 ,  G11C16/32 ,  G11C16/30 ,  G11C16/26

Abstract: A processing device of a memory sub-system is configured to detect a power on event associated with the memory device; scan one or more blocks of a plurality of blocks of the memory device to determine a corresponding time after program (TAP) associated with each block of the one or more blocks; estimate, based on the corresponding TAP of the each block of the one or more blocks, a duration of a power off state preceding the power on event; and update voltage bin assignments of the plurality of blocks associated with the memory device based on the duration of the power off state.

公开(公告)号：US11360677B2

公开(公告)日：2022-06-14

申请号：US16948305

申请日：2020-09-11

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Karl D. Schuh ,  Jiangang Wu ,  Mustafa N. Kaynak ,  Devin M. Batutis ,  Xiangang Luo

IPC: G06F3/06

Abstract: A system includes a memory device having multiple of dice and a processing device operatively coupled to the memory device. The processing device performs operations including receiving memory operations to program sets of pages of data across at least a subset of the plurality of dice and identifying a plurality of the sets of pages experiencing a variation in a data state metric satisfying a threshold criterion. The operations further include partitioning, into a set of partitions, a set of pages of the plurality of the sets of pages, programming the set of partitions to the plurality of dice, and storing, in a metadata table, at least one bit to indicate that the first set of pages is partitioned.

公开(公告)号：US20220147444A1

公开(公告)日：2022-05-12

申请号：US17579966

申请日：2022-01-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Peng Xu ,  Jiangang Wu ,  Yun Li

IPC: G06F12/02 ,  G06F12/0882 ,  G11C11/408 ,  G06F1/3234 ,  G06F12/0873

Abstract: A media management operation is executed to write data from a source block of a cache memory to a set of pages of a destination block of a storage area of a memory sub-system. An entry of a data structure identifying a page count corresponding to the source block of the cache memory is generated. A power loss event associated with the destination block of the storage area is identified. A data recovery operation is executed using the data stored in the source block to complete the write to the destination block. The data is erased from the source block in response to the page count satisfying a condition.

公开(公告)号：US20220091975A1

公开(公告)日：2022-03-24

申请号：US17027895

申请日：2020-09-22

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Vamsi Pavan Rayaprolu ,  Karl D. Schuh ,  Jiangang Wu ,  Gil Golov

IPC: G06F12/02 ,  G06F12/0882 ,  G06F12/0811 ,  G06F12/0873 ,  G06F11/30

Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device can determine a data rate from a first sensor and a data rate from a second sensor. The processing device can write a first set of data received from the first sensor at a first logical block address (LBA) in the memory device. The processing device can write a second set of data received from the second sensor and subsequent to the first set of data at a second LBA in the memory device. The processing device can remap the first LBA and the second LBA to be logically sequential LBAs. The second LBA can be associated with an offset from the first LBA and the offset can correspond to a data rate of the first sensor.

公开(公告)号：US11256616B2

公开(公告)日：2022-02-22

申请号：US16726527

申请日：2019-12-24

Applicant: Micron Technology, Inc.

Inventor： Peng Xu ,  Jiangang Wu ,  Yun Li

IPC: G06F12/02 ,  G06F12/0882 ,  G11C11/408 ,  G06F1/3234 ,  G06F12/0873

Abstract: A media management operation to write data from a source block of a cache memory to a set of pages of a destination block of a storage area of a memory sub-system that is at a higher data density than the cache memory a write request to program data to a memory device of a memory sub-system is executed. An entry of a first data structure identifying a page count corresponding to the source block of the cache memory is generated. Following a determination that the data is written to the set of pages of the destination block of the storage area, the entry is updated to identify a decreased page count corresponding to the source block, where the data is erased from the source block when the decreased page count satisfies a condition. A second entry of a second data structure including information mapping a logical block to the source block of the cache memory is also updated.

公开(公告)号：US20210200682A1

公开(公告)日：2021-07-01

申请号：US16730881

申请日：2019-12-30

Applicant: Micron Technology, Inc.

Inventor： Jiangang Wu ,  Qisong Lin ,  Jung Sheng Hoei ,  Yunqiu Wan ,  Ashutosh Malshe ,  Peng-Cheng Chen

IPC: G06F12/0891 ,  G06F12/0882 ,  G06F12/02 ,  G06F12/0811

Abstract: Methods, systems, and devices for full multi-plane operation enablement are described. A flash controller can determine that a first plane of a set of planes of a memory die is an invalid plane. The flash controller can issue a single descriptor associated with a multi-plane operation for the set of planes of the memory die. The single descriptor can include a plurality of commands for the multi-plane operation in which the first command of the plurality of commands can be a duplicate of a second command of the plurality of commands based on the first plane being the invalid plane. In some cases, a negative-and (NAND) controller can receive the single descriptor associated with the multi-plane operation for the set of planes of a memory die. The NAND controller can issue a plurality of commands for the multi-plane operation based on receiving the single descriptor.

公开(公告)号：US20210191853A1

公开(公告)日：2021-06-24

申请号：US16726527

申请日：2019-12-24

Applicant: Micron Technology, Inc.

Inventor： Peng Xu ,  Jiangang Wu ,  Yun Li

IPC: G06F12/02 ,  G06F12/0882 ,  G06F12/0873 ,  G06F1/3234 ,  G11C11/408

Abstract: A media management operation to write data from a source block of a cache memory to a set of pages of a destination block of a storage area of a memory sub-system that is at a higher data density than the cache memory a write request to program data to a memory device of a memory sub-system is executed. An entry of a first data structure identifying a page count corresponding to the source block of the cache memory is generated. Following a determination that the data is written to the set of pages of the destination block of the storage area, the entry is updated to identify a decreased page count corresponding to the source block, where the data is erased from the source block when the decreased page count satisfies a condition. A second entry of a second data structure including information mapping a logical block to the source block of the cache memory is also updated.

公开(公告)号：US20210181966A1

公开(公告)日：2021-06-17

申请号：US16715986

申请日：2019-12-16

Applicant: Micron Technology, Inc.

Inventor： Peng Xu ,  Jiangang Wu ,  Yun Li

IPC: G06F3/06 ,  G06F12/1009

Abstract: A write request to program data to a memory device of a memory sub-system is received. An intermediate entry of a data structure is generated, the intermediate entry including a pointer identifying a write buffer associated with an intermediate write operation corresponding to the write request. A read request to read the data from the memory device is received and a look-up operation of the data structure is performed to identify the intermediate entry. Using the pointer to locate the write buffer associated with the intermediate write operation. The write buffer is copied to a read buffer associated with the read request and the read request is executed using the read buffer.